Prosecution Insights
Last updated: August 17, 2026
Application No. 18/645,765

INTEGRATED CIRCUIT DEVICE

Non-Final OA §102§103§112
Filed
Apr 25, 2024
Priority
Sep 20, 2023 — RE 10-2023-0125848
Examiner
REIDA, MOLLY KAY
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
360 granted / 435 resolved
+22.8% vs TC avg
Minimal +2% lift
Without
With
+2.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
21 currently pending
Career history
465
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
50.4%
+10.4% vs TC avg
§102
30.1%
-9.9% vs TC avg
§112
17.2%
-22.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 435 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 04/25/2024 has been considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: INTEGRATED CIRCUIT DEVICE INCLUDING NANOSHEETS. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 18-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention and/or Claims 18-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention and/or are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, the written description does not describe the combination of limitations of “the plurality of sub gate portions include a first sub gate portion, a second sub gate portion, a third sub gate portion, and a fourth sub gate portion that are sequentially arranged on the fin top of the fin-type active region” and “a width of the second sub gate portion in the first horizontal direction is greater than a width of the first sub gate portion in the first horizontal direction and the width of the second sub gate portion is less than a width of the third sub gate portion in the first horizontal direction” (emphasis added). Nor does the written description describe the combination of limitations of “the plurality of nanosheets include a first nanosheet between the first sub gate portion and the second sub gate portion, a second nanosheet between the second sub gate portion and the third sub gate portion, a third nanosheet between the third sub gate portion and the fourth sub gate portion, and a fourth nanosheet between the fourth sub gate portion and the main gate portion” and “a width of the fourth nanosheet in the first horizontal direction is greater than a width of the third nanosheet in the first horizontal direction” (emphasis added). That is, the first sub gate portion would be the sub gate portion closest to the active region and the fourth sub gate portion would be the sub gate portion closest to the main gate. This interpretation is consistent with the Specification and the other claims. For example, claim 19 requires the first sub gate portion to have indented side surfaces further providing evidence that the first sub gate portion is intended to be the one closest to the active region. So, while the written description provides several examples including four sub gate portions as required by the claim and the written description provides support for “…a width of the second sub gate portion…is greater than the width of the first sub gate portion…” – there is no support for this limitation in combination with “…the width of the second sub gate portion…is less than a width of the third sub gate portion…”. Furthermore, there is not support for “…a width of the fourth nanosheet…is greater than a width of the third nanosheet…” in any embodiment when interpreting the first sub gate portion being the sub gate portion closest to the active region. Even if one were to interpret the first sub gate portion as being closest to the main gate and the fourth sub gate portion as being closest to the active region – this would still cause issues when it comes to claim 19 which requires the first sub gate portion to have indented side surfaces because every example shows the sub gate portion closest to the main gate as not being indented. In conclusion, the written description does not provide evidence that the Applicant had possession of the claimed invention at the time of filing, nor would it enable one of ordinary skill in the art to make as use the claimed invention. Furthermore, it is unclear what Applicant intends to claim with regard to claims 18-20 and these claims will not be examined further at this time beyond citing the closest prior art related to the Specification. Claim Rejections - 35 USC § 102 (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 7-9, 12 and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (US Pub. 2024/0088264). The applied reference has a common Applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Regarding independent claim 7, Kim teaches an integrated circuit device (Fig. 6; para. 0030+) comprising: a fin-type active region (AP1) extending in a first horizontal direction on a substrate (para. 0032); a channel region (CH1) on the fin-type active region (para. 0034); a gate line (GI/GE) on the fin-type active region, the gate line surrounding the channel region and the gate line extending in a second horizontal direction that crosses the first horizontal direction (para. 0043); and a source/drain region (SD1) on the fin-type active region, the source/drain region being adjacent to the gate line and the source/drain region being in contact with the channel region (para. 0037), wherein the gate line includes a main gate portion (OGE) and a plurality of sub gate portions (PO1, Po2, PO3, PO4) between the main gate portion and the fin-type active region, the main gate portion being at a higher vertical level than the channel region (para. 0043), the plurality of sub gate portions include a first sub gate portion (PO1) on a fin top of the fin-type active region, a second sub gate portion (PO2) on the first sub gate portion, and a third sub gate portion (PO3 or PO4) on the second sub gate portion, a width of the first sub gate portion in the first horizontal direction is less than a width of the second sub gate portion in the first horizontal direction (Fig. 6; para. 0090-0091), the first sub gate portion includes a first side surface and a second side surface overlapping the first side surface in the first horizontal direction (Fig. 6), and the first side surface of the first sub gate portion is indented toward the second side surface of the first sub gate portion (Fig. 6). Re claim 8, Kim teaches wherein the first sub gate portion includes a portion having a width in the first horizontal direction that decreases and thereafter increases at increasing vertical levels of the first sub gate portion (Fig. 6). Re claim 9, Kim teaches wherein the second side surface of the first sub gate portion is indented toward the first side surface of the first sub gate portion (Fig. 6). Re claim 12, Kim teaches wherein the width of the first sub gate portion in the first horizontal direction is equal to a width of the third sub gate portion (PO3) in the first horizontal direction (Fig. 6). Re claim 16, Kim teaches wherein the width of the first sub gate portion in the first horizontal direction is equal to a width of the third sub gate portion (PO3) in the first horizontal direction (Fig. 6). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3, 6, and 17 are rejected under 35 U.S.C. 103 as being obvious over Kim (US Pub. 2024/0088264) in view of Huang et al. (US Pub. 2021/0359142). The applied Kim reference has a common Applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. Regarding independent claim 1, Kim teaches an integrated circuit device (Fig. 6; para. 0030+) comprising: a fin-type active region (AP1) extending in a first horizontal direction on a substrate (para. 0032); a nanosheet stack (CH1) including a plurality of nanosheets (SP1, SP2, SP3, SP4) facing a fin top of the fin-type active region, the nanosheet stack is separated from the fin top of the fin-type active region (Fig. 6; para. 0034); a gate line (GI/GE) on the fin-type active region, the gate line surrounding each of the plurality of nanosheets and the gate line extending in a second horizontal direction that crosses the first horizontal direction (para. 0043); a source/drain region (SD1) on the fin-type active region, the source/drain region being adjacent to the gate line and the source/drain region being in contact with the plurality of nanosheets (para. 0037); and wherein the gate line includes a main gate portion (OGE) on a top surface of the nanosheet stack and a plurality of sub gate portions (PO1, PO2, PO3, PO4) between the main gate portion and the fin-type active region, the plurality of sub gate portions include a first sub gate portion (PO1) on the fin top of the fin- type active region, a second sub gate portion (PO2) on the first sub gate portion, and a third sub gate portion (PO4) on the second sub gate portion, and a width of the first sub gate portion in the first horizontal direction is greater than a width of the third sub gate portion in the first horizontal direction (Fig. 6) and the width of the first sub gate portion is less than a width of the second sub gate portion in the first horizontal direction (Fig. 6; para. 0090-0091). Kim is silent with respect to a backside contact. Huang teaches that backside source/drain contacts are known in the art (para. 0036). It would have been obvious to one of ordinary skill in the art at the time of filing to form a backside contact penetrating the substrate and the backside contact electrically connected to the source/drain region for the purpose of providing the appropriate interconnections to the integrated circuit device. Re claim 3, Kim teaches a fourth sub gate portion (PO3) between the second sub gate portion and the third sub gate portion (Fig. 6), wherein a width of the fourth sub gate portion in the first horizontal direction is greater than the width of the third sub gate portion in the first horizontal direction and the width of the fourth sub gate portion equal to the width of the first sub gate portion in the first horizontal direction (Fig. 6; para. 0090-0091). Re claim 6, Kim teaches wherein the plurality of nanosheets include: a first nanosheet (SP1) between the first sub gate portion and the second sub gate portion; a second nanosheet (SP2) between the second sub gate portion and the third sub gate portion; and a third nanosheet (SP4) between the third sub gate portion and the main gate portion, and a width of the first nanosheet in the first horizontal direction is greater than a width of the second nanosheet in the first horizontal direction (Fig. 6). Re claim 17, Kim is silent with respect to a backside contact. Huang teaches that backside source/drain contacts are known in the art (para. 0036). It would have been obvious to one of ordinary skill in the art at the time of filing to form a backside contact penetrating the substrate and the backside contact electrically connected to the source/drain region for the purpose of providing the appropriate interconnections to the integrated circuit device. Allowable Subject Matter Claims 2, 4, 5, 10, 11, and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Yu et al. (US Pub. 2024/0387668). Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOLLY K REIDA/Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Apr 25, 2024
Application Filed
Jun 20, 2024
Response after Non-Final Action
Jul 28, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12690321
DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME
3y 9m to grant Granted Jul 21, 2026
Patent 12684823
LAYER STRUCTURES INCLUDING CONFIGURATION INCREASING OPERATION CHARACTERISTICS, METHODS OF MANUFACTURING THE SAME, ELECTRONIC DEVICES INCLUDING LAYER STRUCTURES, AND ELECTRONIC APPARATUSES INCLUDING ELECTRONIC DEVICES
4y 1m to grant Granted Jul 14, 2026
Patent 12672279
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 4m to grant Granted Jun 30, 2026
Patent 12666590
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
3y 6m to grant Granted Jun 23, 2026
Patent 12660161
CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
3y 1m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
85%
With Interview (+2.2%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 435 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month