Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18645785 filed on 04/25/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of 1-2, 4-5, 12-15 in the reply filed on 07/14/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 4, 13-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 2, 4, 13-14 recite the limitations “a floating region”, “two spaced floating regions”. The metes and bounds of the claimed limitation can not be determined for the following reasons: the specification and drawing of Fig. 4 discloses that the floating regions 20 are connected to ohmic contact 21. Accordingly, it is unclear how element 20 is considered floating.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ni et al. (CN 111627983 A).
Regarding independent claim 1, Ni et al. teach a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), comprising:
a SiC semiconductor substrate (Fig. 2, element 1);
a drift layer (Fig. 2, element 3) located on the SiC semiconductor substrate;
a fin-shaped channel layer (Fig. 2, element 14) located on the drift layer;
a source region (Fig. 2, element 5) located on the fin-shaped channel layer; and
a first insulated isolating layer (Figs. 2 & 8, bottom portion of element 15) located on a portion of the drift layer, and wherein the portion of the drift layer is not covered by the fin-shaped channel layer (Figs. 1-3),
wherein the fin-shaped channel layer and the source region are of a stacking structure (Fig. 2), and the SiC MOSFET further comprising:
a gate electrode (Fig. 2, element 4),
wherein the gate electrode is located on the first insulated isolating layer and wherein the gate electrode is separately located on two sides of the stacking structure (Fig. 2);
a gate oxide layer (Figs. 2 & 8, vertical portion of element 15) located between the gate electrode and the stacking structure;
a second insulated isolating layer (Figs. 2 & 7, element 16) that covers an external side wall and an upper surface of the gate electrode;
a source electrode (Figs. 2 & 8, element 18) that covers the first insulated isolating layer, the second insulated isolating layer, and the source region; and
a drain electrode (Figs. 2 & 8, element 17) located on a side of the SiC semiconductor substrate, and the side of the SiC semiconductor substrate faces away from the drift layer.
Regarding claim 2, Ni et al. teach a floating region (Fig. 2, element 7), wherein the floating region is located on the drift layer and wherein the floating region is separately located on two sides of the fin-shaped channel layer.
Regarding claim 4, Ni et al. teach wherein at least two spaced floating regions are separately disposed on the two sides of the fin-shaped channel layer (Fig. 2), the SiC MOSFET further comprising: a groove (Figs. 2 & 3, where element 9 is formed), wherein the groove extends in the two sides of the fin-shaped channel layer and wherein the groove penetrates through the first insulated isolating layer and a part of the drift layer, wherein the groove is located between adjacent floating regions; and a schottky contact (Fig. 2, element 9 forms Schottky contact) portion that is padded in the groove.
Regarding claim 5, Ni et al. teach wherein a material of the gate electrode comprises polycrystalline silicon (specification discloses polysilicon).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ni et al. (CN 111627983 A) in view of Raring et al. (US 9,666,677).
Regarding independent claim 12, Ni et al. teach an integrated circuit, comprising:
a SiC MOSFET comprising:
a SiC semiconductor substrate (Fig. 2, element 1);
a drift layer (Fig. 2, element 3) located on the SiC semiconductor substrate;
a fin-shaped channel layer (Fig. 2, element 14) located on the drift layer;
a source region (Fig. 2, element 5) located on the fin-shaped channel layer; and
a first insulated isolating layer (Figs. 2 & 8, bottom portion of element 15) located on a portion of the drift layer, wherein the fin-shaped channel layer does not cover the first insulated isolating layer (Figs. 1-3),
wherein the fin-shaped channel layer and the source region are of a stacking structure (Fig. 2),
the SiC MOSFET further comprising:
a gate electrode (Fig. 2, element 4), wherein the gate electrode is located on the first insulated isolating layer and wherein the gate electrode is separately located on two sides of the stacking structure (Fig. 2);
a gate oxide layer (Figs. 2 & 8, vertical portion of element 15) located between the gate electrode and the stacking structure;
a second insulated isolating layer (Figs. 2 & 7, element 16) that covers an external side wall and an upper surface of the gate electrode;
a source electrode (Figs. 2 & 8, element 18) that covers the first insulated isolating layer, the second insulated isolating layer, and the source region; and
a drain electrode (Figs. 2 & 8, element 17) located on a side of the SiC semiconductor substrate, and wherein the side of the SiC semiconductor substrate is separated from the drift layer.
Ni et al. do not explicitly disclose a circuit board.
It is well known in the art to form semiconductor devices on circuit board as shown by Raring et al. (Fig. 11n, “FIG. 11n is a simplified schematic cross-section of a structure of a plurality of HEMT devices selectively bonded to multiple carrier wafers or printed circuit boards”).
Regarding claim 13, Ni et al. teach a floating region (Fig. 2, element 7), wherein the floating region is located on the drift layer and wherein the floating region is separately located on two sides of the fin-shaped channel layer.
Regarding claim 14, Ni et al. teach the SiC MOSFET further comprising: a groove (Figs. 2 & 3, where element 9 is formed), wherein the groove is located on the two sides of the fin-shaped channel layer, and wherein the groove penetrates through the first insulated isolating layer and a part of the floating region; and an ohmic contact portion (Fig. 2, element 9 forms ohmic contact) that is padded in the groove.
Regarding claim 15, Ni et al. teach wherein at least two spaced floating regions are separately disposed on the two sides of the fin-shaped channel layer (Fig. 2), the SiC MOSFET further comprising: a groove (Figs. 2 & 3, where element 9 is formed), wherein the groove is located on the two sides of the fin-shaped channel layer and wherein the groove penetrates through the first insulated isolating layer and a part of the drift layer, wherein the groove is located between adjacent floating regions; and a schottky contact portion (Fig. 2, element 9 forms schottky contact) that is padded in the groove.
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813
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