Prosecution Insights
Last updated: October 02, 2026
Application No. 18/645,813

SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Apr 25, 2024
Priority
May 11, 2023 — JP 2023-078808
Examiner
REIDA, MOLLY KAY
Art Unit
Tech Center
Assignee
Sumitomo Electric Industries Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
366 granted / 444 resolved
+22.4% vs TC avg
Minimal +3% lift
Without
With
+3.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
15 currently pending
Career history
468
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
50.6%
+10.6% vs TC avg
§102
29.9%
-10.1% vs TC avg
§112
17.3%
-22.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 444 resolved cases

Office Action

§102
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of Invention I (claims 1-12) in the reply filed on 07/24/2026 is acknowledged. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 04/25/2024 has been considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: HIGH ELECTRON MOBILITY SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 6, 8, 9, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okamoto et al. (JP2017-085059A). Regarding independent claim 1, Okamoto teaches a semiconductor device (Fig. 4; para. 0013+), comprising: a substrate (1) (para. 0014); a semiconductor layer (2) on the substrate (para. 0014); a first main electrode (4) and a second main electrode (5) that are on the semiconductor layer (para. 0019); a control electrode (8) that is on the semiconductor layer and is between the first main electrode and the second main electrode (para. 0027); a first insulating layer (7) that is in direct contact with the control electrode and covers the first main electrode (para. 0026); a second insulating layer (9) on the first insulating layer (para. 0030); a first conductive layer that penetrates the first insulating layer and the second insulating layer, is electrically connected to the first main electrode, and is in direct contact with the first insulating layer (portion of 11/12 within via 10 connected to source 4; para. 0031-0033); and a second conductive layer that is on the second insulating layer and is in direct contact with the first conductive layer (portion of 11/12 above layer 9 connected to source electrode 4; para. 0031-0033), wherein the first insulating layer includes aluminum nitride (para. 0026). Re claim 2, Okamoto teaches wherein the first insulating layer is in direct contact with the semiconductor layer (Fig. 4). Re claim 3, Okamoto teaches wherein resistance of the first insulating layer to etching using a fluorine-containing reactive gas is higher than resistance of the second insulating layer to etching using the fluorine-containing reactive gas (this is true for the disclosed materials of the first insulating layer (para. 0026) and the second insulating layer (para. 0030)). Re claim 4, Okamoto teaches a third insulating layer (leftmost 6) that is between the first main electrode and the first insulating layer and that the first conductive layer penetrates (para. 0022), wherein resistance of the third insulating layer to etching using a chlorine-containing reactive gas is higher than resistance of the first insulating layer to etching using the chlorine-containing reactive gas (para. 0022, 0026 – at least some of the disclosed combinations of materials would meet this limitation). Re claim 6, Okamoto teaches wherein the first main electrode includes a third conductive layer (4b) that is in direct contact with the first conductive layer and the third insulating layer (para. 0021), and resistance of the third conductive layer to etching using a fluorine-containing reactive gas is higher than resistance of the third insulating layer to etching using the fluorine-containing reactive gas (etching aluminum (which is what 4b is made from) using fluorine-containing reactive gases is not very effective; however, using fluorine-containing reactive gases for the removal of the third insulating layer materials; for example, aluminum nitrides or oxides (para. 0022), is generally effective; therefore, the limitations of claim 6 are considered to be met by Okamoto). Re claim 8, Okamoto teaches a fourth conductive layer that penetrates the first insulating layer and the second insulating layer, is electrically connected to the second main electrode, and is in direct contact with the first insulating layer (portion of 11/12 within via 10 connected to drain 5; para. 0031-0033); and a fifth conductive layer that is on the second insulating layer and is in direct contact with the fourth conductive layer (portion of 11/12 above layer 9 connected to drain 5; para. 0031-0033). Re claim 9, Okamoto teaches a fourth insulating layer (rightmost 6) that is between the second main electrode and the first insulating layer and that the fourth conductive layer penetrates, wherein resistance of the fourth insulating layer to etching using a chlorine-containing reactive gas is higher than resistance of the first insulating layer to etching using the chlorine-containing reactive gas (para. 0022, 0026 – at least some of the disclosed combinations of materials would meet this limitation). Re claim 11, Okamoto teaches wherein the second main electrode includes a sixth conductive layer (5b) that is in direct contact with the fourth conductive layer and the fourth insulating layer (para. 0021), and resistance of the sixth conductive layer to etching using a fluorine-containing reactive gas is higher than resistance of the fourth insulating layer to etching using the fluorine-containing reactive gas (etching aluminum (which is what 4b is made from) using fluorine-containing reactive gases is not very effective; however, using fluorine-containing reactive gases for the removal of the third insulating layer materials; for example, aluminum nitrides or oxides (para. 0022), is generally effective; therefore, the limitations of claim 6 are considered to be met by Okamoto). Allowable Subject Matter Claims 5, 7, 10, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOLLY K REIDA/Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Apr 25, 2024
Application Filed
Sep 25, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12690321
DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME
3y 9m to grant Granted Jul 21, 2026
Patent 12684823
LAYER STRUCTURES INCLUDING CONFIGURATION INCREASING OPERATION CHARACTERISTICS, METHODS OF MANUFACTURING THE SAME, ELECTRONIC DEVICES INCLUDING LAYER STRUCTURES, AND ELECTRONIC APPARATUSES INCLUDING ELECTRONIC DEVICES
4y 1m to grant Granted Jul 14, 2026
Patent 12672279
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 4m to grant Granted Jun 30, 2026
Patent 12666590
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
3y 6m to grant Granted Jun 23, 2026
Patent 12660161
CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
3y 1m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
86%
With Interview (+3.2%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 444 resolved cases by this examiner. Grant probability derived from career allowance rate.

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