Prosecution Insights
Last updated: July 17, 2026
Application No. 18/645,851

MULTILAYER MOISTURE REPELLING FILMS FOR FRONT END FET APPLICATIONS

Non-Final OA §103
Filed
Apr 25, 2024
Priority
May 02, 2023 — provisional 63/499,579
Examiner
ERDEM, FAZLI
Art Unit
Tech Center
Assignee
Qorvo US Inc.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
918 granted / 1075 resolved
+25.4% vs TC avg
Strong +16% interview lift
Without
With
+15.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
36 currently pending
Career history
1099
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
62.4%
+22.4% vs TC avg
§102
30.5%
-9.5% vs TC avg
§112
3.7%
-36.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1075 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kalliomaki (20240410052) in view of Barney (20210387259). Regarding Claim 1, in Figs. 1A-3B and in pareagraphs 0043, 0045, 0165 and 0166, Kalliomaki discloses an integrated circuit (IC) structure, the IC structure comprising: a semiconductor substrate 20 having an active region (OLED); a contact (OLED contact) positioned over the active region; and an organic film that covers the contact. Kalliomaki fails to disclose the APHO (aminated polyhydroxide) film. However, Barney discloses an ALD/MLD coating process where in paragraphs 0010, 0013, 0041, 0043, 0046, 0047, 0049, 0051, 0060, 0063, 0090, 0094, 0096 and 0100, the required aminated polyhydroxy (ald/mld coated/deposited organic polymer) is disclosed. It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the require aminated polyhydroxy in Kalliomaki as taught by Barney in order to coat/deposit inorganic/organic film/layer in repetitive additive configuration. Regarding Claim 2, in Barney, the APHO film has the claimed structure. Regarding Claim 3, in Kalliomaki, a second active region and a second contact, (OLED) wherein: the active region is a first active region; the contact is a first contact; the semiconductor substrate has the second active region; the second contact is formed over the second active region; Furthermore. in Barney, APHO film does not cover the second contact as Barney discloses way of coating or not coating semiconductor device elements. Regarding Claim 4, in Kalliomaki, a third active region and a third contact (OLED) wherein: the semiconductor substrate has the third active region; the third contact is formed over the third active region. Furthermore, in Barney, APHO film does not cover the third contact; and the first active region is positioned between the second active region and the third active region as Barney discloses way of coating or not coating semiconductor device elements. Regarding Claim 5, in Kalliomaki, the second active region is a first drain/source region; the third active region is a second drain/source region; the first active region is a channel region; wherein the first active region, the second active region, the third active region, the first contact, the second contact, and the third contact form a field effect transistor (FET); wherein the semiconductor substrate defines a top surface; and wherein, with respect to the FET (OLED device). Furthermore, since Barnes teaches a method of coating or not coating portions of a semiconductor device for example, the APHO film covers approximately only the first contact and portions of the top surface of the channel region but not the second contact, the third contact, nor other portions of the top surface for the FET. Regarding Claim 6, in Kalliomaki, the first contact is a second metallic contact, the third contact is a second metallic contact, and the first contact is a gate contact. Regarding Claim 7, in Kalliomaki, the first contact is formed on the first active region; the second contact is formed on the second active region; and the third contact is formed on the third active region. Regarding Claim 8, in Barney, the APHO film exhibits moisture repelling properties of less than 104 grams per square meter per day. Regarding Claim 9, in Barney, the APHO film has a thickness of between 1 and 2 microns (additive coating) Regarding Claim 10, in Barney, the APHO film has a thickness of between 1 and 2 microns (additive coating) Regarding Claim 11, in Barney, the APHO film has a dielectric constant less than or equal to 2.1 (additive coating). Furthermore, Kalliomaki’s device could be oriented to arrive at the required dielectric constant. Regarding Claim 12, in Barney, APHO film has a transition temperature equal to or greater than 250 degrees Celsius. Regarding Claim 13, in Figs. 1A-3B and in paragraphs 0043, 0045, 0165 and 0166, Kalliomaki discloses a method of manufacturing an integrated circuit (IC) structure, the method comprising: providing a semiconductor substrate having an active region (OLED); providing a contact positioned over the active region; and forming an organic film that covers the contact. Kalliomaki fails to disclose the APHO (aminated polyhydroxide) film. However, Barney discloses an ALD/MLD coating process where in paragraphs 0010, 0013, 0041, 0043, 0046, 0047, 0049, 0051, 0060, 0063, 0090, 0094, 0096 and 0100, the required aminated polyhydroxy (ald/mld coated/deposited organic polymer) is disclosed. It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the require aminated polyhydroxy in Kalliomaki as taught by Barney in order to coat/deposit inorganic/organic film/layer in repetitive additive configuration. Regarding Claim 14, in Kalliomaki, forming the organic film that covers the contact comprises:(a) performing atomic layer deposition (ALD) to deposit an Al203 layer or a SiO2 layer; or (b) performing molecular layer deposition (MLD) to deposit a hydroxy- carbon polymer layer. Furthermore, Barney discloses APHO film. Regarding Claim 15, in Barney, repeating (a) and (b) until the APHO film has a thickness of between 1 and 2 microns (additive process) Regarding Claim 16, in Kalliomaki, the active region is a channel region; and the contact is a gate contact (OLED) Regarding Claim 17, in Kalliomaki, the organic film further covers a portion of a top surface of the semiconductor substrate over the channel region. Furthermore, Barney discloses the APHO film. Regarding Claim 18, in Kalliomaki, the semiconductor substrate defines a surface; the active region is a channel region; the contact is a gate contact formed over the channel region; the semiconductor substrate defines a first drain/source region and a second drain/source region; a first drain/source contact is formed over the second drain/source region; a second drain/source contact is formed over the first drain/source region; wherein the channel region is positioned between the first drain/source region and the second drain/source region; wherein the first drain/source region, the first drain/source contact, the second drain/source region, the second drain/source contact, the channel region, and the gate contact form a field effect transistor (FET) (OLED) Regarding Claim 19, in Kalliomaki forming the organic film that covers the contact comprises: forming the organic film so that the organic film covers the first drain/source contact of the FET, the gate contact of the FET, the second drain/source contact of the FET, and the surface of the semiconductor substrate; an detching the organic film so that, with respect to the FET, the organic film covers approximately only the gate contact and a portion of the surface over the channel region and not the first drain/source contact, the second drain/source contact, nor other portions of the surface of the semiconductor substrate of the FET. Furthermore, Barney discloses APHO film and coating or not coating portions of the semiconductor device. Regarding Claim 20, in Barney, APHO film has a thickness of between 1 and 2 microns (additive coating). Examiner is including following pertinent prior art references that are NOT RELIED UPON but that disclose ALD/MLD combined coating/deposition of organic polymers to protect the contacts of the semiconductor device from moisture/corrosion. Bojkov 20180122716 Bojkov 20220123216 Georget 20100178481 Guo 20160133689 Yang 20240215346 Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAZLI ERDEM/Primary Examiner, Art Unit 2812 6/18/2026
Read full office action

Prosecution Timeline

Apr 25, 2024
Application Filed
Jun 23, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+15.9%)
2y 5m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1075 resolved cases by this examiner. Grant probability derived from career allowance rate.

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