DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I and Species A in the reply filed on 30 July 2026 is acknowledged.
Claims 4, 10 and 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II or Species B, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 30 July 2026.
Information Disclosure Statements
The Information Disclosure Statements (IDS) submitted on 25 April 2024, 1 October 2024, and 1 April 2026 have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, and 7-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshida (US 20220254804 A1, hereinafter “Yoshida”).
Regarding Claim 1 - Yoshida discloses a three-dimensional memory device, comprising: alternating stacks of insulating layers (132L and 232L [0085] and Fig. 18D) and electrically conductive layers (146 and 246 [0147] and Fig. 18D), wherein each of the alternating stacks laterally extends along a first horizontal direction (WLR [0150] extending in hd1 [0084] and Fig. 18B), and the alternating stacks are laterally spaced apart from each other along a second horizontal direction (WLR separated by trenches 179 [0150] in hd2 [0084] and Fig. 18B) by lateral isolation trenches (179 [0137] and Fig. 18B); arrays of memory openings, wherein each array of memory openings vertically extends through a respective one of the alternating stacks (41 [0098] and Figs. 5A and 5B, and 43 [0115] and Figs. 8A and 8B); arrays of memory opening fill structures located within the arrays of memory openings (58 [0132] and Figs. 12D and 13A), wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements (50 [0131] and Fig. 12D) and a vertical semiconductor channel (60 [0132] and Fig. 12D); and composite lateral isolation trench fill structures located in the lateral isolation trenches (Combination of 220 and 776 [0188] and Fig. 35), wherein each of the composite lateral isolation trench fill structures comprises a laterally alternating sequence of dielectric pillar structures (220 [0188] and Fig. 35) and dielectric containing structures arranged along the first horizontal direction (776 extended in the hd1 direction [0188] and Fig. 35).
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Regarding Claim 2 - Yoshida further discloses the three-dimensional memory device of Claim 1, wherein the dielectric containing structures comprise isolation opening fill structures (776 fills openings 779, which may have the same shape as 179 [0179], which is filled by 176 [0155]).
Regarding Claim 3 - Yoshida further discloses the three-dimensional memory device of Claim 2, wherein each of the dielectric pillar structures comprises a pair of laterally-concave and vertically-straight sidewalls in contact with a respective pair of the isolation opening fill structures (Sidewalls of 220 in contact with two 776s [0188] and Fig. 37).
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Regarding Claim 5 - Yoshida further discloses the three-dimensional memory device of Claim 3, further comprising support pillar structures vertically extending through and laterally surrounded by a respective one of the alternating stacks (20 [0120] and Fig. 11D).
Regarding Claim 7 - Yoshida further discloses the three-dimensional memory device of Claim 3, wherein each of the isolation opening fill structures comprises a pair of first-type laterally-convex and vertically-straight sidewalls in contact with the respective pair of laterally-concave and vertically-straight sidewalls of the dielectric pillar structures (176 is seen as laterally convex in Fig. 18B in direction hd1, and vertically straight in Fig. 18C).
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Regarding Claim 8 - Yoshida further discloses the three-dimensional memory device of Claim 7, wherein each of the isolation opening fill structures further comprises at least two second-type laterally-convex and vertically-straight sidewalls in contact with a respective one of the alternating stacks (176 is convex in hd2 [0196] and seen as laterally convex in Fig. 18B in direction hd2, and vertically straight in Fig. 34A).
Regarding Claim 9 - Yoshida further discloses the three-dimensional memory device of Claim 8,
wherein: the at least two second-type laterally-convex and vertically-straight sidewalls comprise two laterally-undulating lengthwise sidewalls (176 described in [0196] and seen as laterally undulating in Fig. 18B in direction hd2); and each of the two laterally-undulating lengthwise sidewalls comprises a respective plurality of second-type laterally-convex and vertically-straight sidewalls that are adjoined to each other at vertically-extending edges (176 as described in [0196]).
Regarding Claim 11 - Yoshida further discloses the three-dimensional memory device of Claim 2,
wherein: each of the dielectric pillar structures has a first lateral extent along the second horizontal direction (W1 in annotated Fig. 37); and each of the isolation opening fill structures has a second lateral extent along the second horizontal direction that is different from the first lateral extent (W2 in annotated Fig. 37).
Regarding Claim 12 - Yoshida further discloses the three-dimensional memory device of Claim 2,
wherein each of the dielectric pillar structures and the isolation opening fill structures vertically extends at least from a first horizontal plane including bottommost surfaces of the alternating stacks to a second horizontal plane including topmost surfaces of the alternating stacks (From semiconductor layer 110 [0085] to above topmost 246 and 232L as shown in Figs. 34A and 34B).
Regarding Claim 13 - Yoshida further discloses the three-dimensional memory device of Claim 2, wherein: each of the alternating stacks comprises a first-tier alternating stack of first insulating layers and first electrically conductive layers (132L and 146) and a second-tier alternating stack of second insulating layers and second electrically conductive layers (232L and 246); and each of the dielectric pillar structures comprises a vertical stack including a first-tier dielectric pillar vertically extending through the first-tier alternating stack (220A [0189] and Fig. 38) and a second-tier dielectric pillar vertically extending through the second-tier alternating stack and contacting a top surface of the first-tier dielectric pillar (220B [0189] and Fig. 38).
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Regarding Claim 14 - Yoshida further discloses the three-dimensional memory device of Claim 13, wherein each of the isolation opening fill structures continuously extends from a horizontal plane including bottommost surfaces of the first-tier alternating stacks at least to a horizontal plane including topmost surfaces of the second-tier alternating stacks as a single continuous material portion having a homogenous material composition throughout (176 extends from semiconductor layer 110 [0085] to above topmost 246 and 232L as shown in annotated Fig. 34A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 20220254804 A1, hereinafter “Yoshida”), in view of the following argument.
Regarding Claim 6 - Yoshida further discloses all the limitations of claim 5.
Yoshida fails to disclose the dielectric pillar structures and the support pillar structures comprise a first dielectric fill material; and the isolation opening fill structures comprise a fill material that is formed separately from the first dielectric fill material.
However, Claim 6 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed isolation opening fill structures need not be formed by the process of a fill material formed separately from the first dielectric fill material. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983). See MPEP 2113.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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