DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Applicant’s election of and species I, drawn to Figures 1-5 and claims 1-5, is acknowledged. Claims 6-11, drawn to an unelected species, are thus withdrawn from further examination. Claims 1-5 are examined herein.
Election/Restrictions
Claims 6-11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/28/2026.
Applicant’s election without traverse of species I, drawn to Figures 1-5 and claims 1-5, in the reply filed on 07/28/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/25/2024 is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show the input part and output part in Figure 2 as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
The second paragraph labeled [0001] should be labeled [0002].
The third paragraph labeled [0002] should be labeled [0003].
The fourth paragraph labeled [003] should be labeled [004].
Appropriate correction is required.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kinouchi (Japanese Patent Application Publication JP2000311983A).
Regarding claim 1, Kinouchi (Japanese Patent Application Publication JP2000311983A) teaches a semiconductor module (IGBT module, Figures 1 & 7 & 9) comprising: a first semiconductor switching element (IGBT element 5 or fee wheel diode element 4, Figures 1 & 7 & 9, paragraphs 0020) including a first input electrode (lower electrode, Figures 1 & 7 & 9, paragraph 0006-0007 + 0020) and a first output electrode (emitter electrode 10 or anode electrode 9, Figures 1 & 7 & 9, paragraph 0023); a second semiconductor switching element (IGBT element 5 or fee wheel diode element 4, Figures 1 & 7 & 9, paragraphs 0020) including a second input electrode (lower electrode, Figures 1 & 7 & 9, paragraph 0006-0007 + 0020) and a second output electrode (emitter electrode 10 or anode electrode 9, Figures 1 & 7 & 9, paragraph 0023); an input part (collector electrode 8 or collector conductor 8, Figures 1 & 7 & 9, paragraphs 0005-0006 + 0020) configured to receive an input of current; a first connection part (collector wiring 3 + balance control element 11, Figures 1 & 7 & 9, paragraphs 0006-0007 + 0020) configured to electrically connect the first input electrode and the input part; a second connection part (collector wiring 3 + balance control element 11, Figures 1 & 7 & 9, paragraphs 0006-0007 + 0020) configured to electrically connect the second input electrode and the input part; and an output part (emitter electrode 7 or emitter conductor 7, Figures 1 & 7 & 9, paragraphs 0005 + 0007 + 0020) electrically connected (bonding wire 6, Figures 1 & 7 & 9, paragraphs 0005-0006) to the first output electrode and the second output electrode, wherein each of the first connection part and the second connection part includes, as a current path, a variable resistive member (balance control element 11, Figures 1 & 7 & 9, paragraphs 0020-0021 + 0023-0028) comprising material with a positive temperature resistance coefficient higher than a temperature resistance coefficient of material of the input part, as claimed.
Regarding claim 2, Kinouchi (Japanese Patent Application Publication JP2000311983A) teaches the semiconductor module according to claim 1, as claimed. Kinouchi (Japanese Patent Application Publication JP2000311983A) further teaches further comprising a substrate (insulating substrate 2, Figures 1 & 7 & 9, paragraphs 0005 + 0020) configured to support the first semiconductor switching element and the second semiconductor switching element, wherein each of the first connection part and the second connection part comprises a conductor pattern (collector wiring 3, Figure 1 & 7 & 9, paragraphs 0005-0007 + 0020-0021) provided on the substrate, as claimed.
Regarding claim 3, Kinouchi (Japanese Patent Application Publication JP2000311983A) teaches the semiconductor module according to claim 2, as claimed. Kinouchi (Japanese Patent Application Publication JP2000311983A) further teaches wherein the first connection part includes: a first pad (Figure 1 or 7 or 9) electrically connected to the first input electrode, and a first wiring (collector wiring 3, Figures 1 & 7 & 9, paragraph 0006) configured to electrically connect the input part and the first pad, the second connection part includes: a second pad (Figure 1 or 7 or 9) electrically connected to the second input electrode, and a second wiring (collector wiring 3, Figures 1 & 7 & 9, paragraph 0006) configured to electrically connect the input part and the second pad, and each of the first wiring and the second wiring includes the variable resistive member, which comprises material with a positive temperature resistance coefficient higher than the temperature resistance coefficient of the material of the input part.
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Regarding claim 4, Kinouchi (Japanese Patent Application Publication JP2000311983A) teaches the semiconductor module according to claim 3, as claimed. Kinouchi (Japanese Patent Application Publication JP2000311983A) further teaches wherein the variable resistive member comprises nickel or nickel alloy (paragraph 0024), as claimed.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: the prior art of record does not teach or suggest the combination of the cross-sectional area, represented as S, and the length, represented as L, of the variable resistive member having a relation satisfied by 10 ≤ L/S ≤ 25.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM M MOHAMED-ALY whose telephone number is (571)270-0312. The examiner can normally be reached Monday – Friday 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREEM M MOHAMED-ALY/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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