DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant’s election without traverse of Species I (i.e., Claims 1-8 and 10-20) in the reply filed July 23rd, 2026, is acknowledged. Therefore, pursuant to said response, Claim 9 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Status of Claims
Claims 1-20 are pending; however, as stated above, Claim 9 has been withdrawn. Therefore, Claims 1-8 and 10-20 are subject to the below examination on the merits.
Information Disclosure Statement
No information disclosure statement has been provided by Applicant.
Drawings
The drawings are objected to because shading is used improperly in the drawing, reducing its reproducibility. 37 CFR 1.84(m) requires that shading should not reduce legibility, solid black shading is not used except for bar graphs and color, and that shading with spaced lines is preferred. More specifically, the shading of elements #17, 21, 23, 25, and 27 is reducing the legibility of the figures and, upon reproduction, could cause clarity issues.
The drawings are additionally objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
a) Reference Character 131 (as disclosed in Figs. 8 and 11)
b) Reference Character 181 (as disclosed in Figs. 8 and 11)
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested, “MULTI-PACKAGE STRUCTURE WITH A FLEXIBLE INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF”.
The specification is objected to as it fails to include a brief summary of the invention as required by MPEP § 608.01(d) and 37 CFR 1.73, cited below:
(h) BRIEF SUMMARY OF THE INVENTION: See MPEP § 608.01(d). A brief summary or general statement of the invention as set forth in 37 CFR 1.73. The summary is separate and distinct from the abstract and is directed toward the invention rather than the disclosure as a whole. The summary may point out the advantages of the invention or how it solves problems previously existent in the prior art (and preferably indicated in the Background of the Invention). In chemical cases it should point out in general terms the utility of the invention. If possible, the nature and gist of the invention or the inventive concept should be set forth. Objects of the invention should be treated briefly and only to the extent that they contribute to an understanding of the invention.
Appropriate correction is required.
The specification is further objected to as the section headings are bolded. Pursuant to MPEP § 608.01(a) and 37 CFR 1.77:
(c) The text of the specification section defined in paragraphs (b)(1) through (b)(12) of this section, if applicable, should be preceded by a section heading in uppercase and without underlining or bold type. (emphasis added)
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4, 7, and 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park, et al. (US 2025/0201685 A1; hereinafter referred to as Park) and further in view of Im (US 2017/0117215 A1; hereinafter referred to as Im).
Regarding Claim 1, Park discloses a package structure (semiconductor package 10, [0023], Fig. 2), comprising:
a substrate (package substrate 100, [0023], Fig. 2);
a first interposer bonded to the substrate (interposer 200a, [0023], Fig. 2);
a second interposer bonded to the substrate and spaced apart from the first interposer (interposer 200b, [0023], Fig. 2);
a first semiconductor die bonded to the first interposer (chip 250a, [0023], Fig. 2);
a second semiconductor die bonded to the second interposer (chip 250b, [0023], Fig. 2); and
an interconnect structure bonded to the first interposer and the second interposer (connection chip 300, [0023], Fig. 2).
Park fails to explicitly disclose that the interconnect structure is a flexible interconnect structure.
However, in analogous art, Im discloses a flexible interconnect structure (Im: semiconductor device 10, Fig. 1E; said semiconductor device 10 showcases the entirety of the bridge structure, with semiconductor chips 110 being analogous to the instant application’s first and second bridge die and interconnection 165 being analogous to the instant application’s flexible substrate).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the package structure as disclosed by Park such that the interconnect structure was flexible as disclosed by Im. One would be motivated to do so because the use of a flexible interconnect allows for the two interposers/dies to be connected to one another while being disposed on a non-flat surface (e.g., the dies can be at uneven/different heights) which increases device reliability in wearable devices (Im: [0054]).
Regarding Claim 2, Park/Im discloses the package structure as claimed in claim 1, wherein in a top view, the flexible interconnect structure partially overlaps the first interposer and the second interposer (Park: Fig. 1; connection chip 300 partially overlaps the first and second interposer 200a/b) and is separated from the first semiconductor die and the second semiconductor die (Park: Fig. 1; connection chip 300 is separated from chips 250a/b).
Regarding Claim 3, Park/Im discloses the package structure as claimed in claim 1, wherein in a sectional view, the first interposer and the second interposer are located between the flexible interconnect structure and the substrate (Park: Fig. 2; interposers 200a/b are located between connection chip 300 and package substrate 100).
Regarding Claim 4, Park/Im discloses the package structure as claimed in claim 1, wherein:
the first interposer comprises:
a plurality of first bonding pads bonded to the first semiconductor die (Park: first bonding pads 232, [0044], Fig. 2); and
a plurality of first conductors bonded to the flexible interconnect structure (Park: third solder bumps 270c, [0055], Fig. 2; “third solder bumps 270c may have a stacked structure of a copper pillar, a micro solder, and a copper pillar”, therefore, are analogous to the first conductors of the instant application),
the second interposer comprises:
a plurality of second bonding pads bonded to the second semiconductor die (Park: first bonding pads 232, [0044], Fig. 2); and
a plurality of second conductors bonded to the flexible interconnect structure (Park: third solder bumps 270c, [0055], Fig. 2; “third solder bumps 270c may have a stacked structure of a copper pillar, a micro solder, and a copper pillar”, therefore, are analogous to the first conductors of the instant application),
in a top view, the plurality of first conductors are located outside an orthogonal projection of the first semiconductor die on the substrate (Park: Fig. 1; the connection chip is outside of the orthogonal projection of the first semiconductor die, and the third solder bumps 270c do not appear beyond the connection chip; therefore, the third solder bumps 270c would also be located outside the orthogonal projection of the first semiconductor die), and
in the top view, the plurality of second conductors are located outside an orthogonal projection of the second semiconductor die on the substrate (Park: Fig. 1; the connection chip is outside of the orthogonal projection of the second semiconductor die, and the third solder bumps 270c do not appear beyond the connection chip; therefore, the third solder bumps 270c would also be located outside the orthogonal projection of the second semiconductor die).
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Regarding Claim 7, Park/Im discloses the package structure as claimed in claim 1, wherein the flexible interconnect structure comprises:
a first bridge die (Im: semiconductor chip 110, see Annotated Fig. 1A);
a second bridge die (Im: semiconductor chip 110, see Annotated Fig. 1A);
a flexible substrate, wherein the first bridge die and the second bridge die are respectively adjacent to opposite ends of the flexible substrate (Im: interconnection 165, [0019], Fig. 1A);
a plurality of conductive lines disposed on the flexible substrate and electrically connecting the first bridge die to the second bridge die (Im: redistribution lines 130, [0023], Fig. 1A); and
a plurality of conductive bumps (Im: external terminals 150, [0024], Fig. 1A; Park: third chip pads 320, [0055]), wherein the first bridge die and the second bridge die are respectively bonded to the first interposer and the second interposer through the plurality of conductive bumps (Park: Fig. 2).
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Regarding Claim 12, Park discloses a package structure (semiconductor package 10, [0023], Fig. 2), comprising:
a substrate (package substrate 100, [0023], Fig. 2);
a first package bonded to the substrate (first package, see Annotated Fig. 15);
a second package bonded to the substrate and adjacent to the first package (second package, see Annotated Fig. 15), wherein the first package has a first depression adjacent to the second package (first depression, see Annotated Fig. 15), and the second package has a second depression adjacent to the first depression (second depression, see Annotated Fig. 15); and
an interconnect structure located in the first depression and the second depression and electrically connecting the first package to the second package (connection chip 300, [0023], Figs. 1 and 17).
Park fails to explicitly disclose that the interconnect structure can be a flexible interconnect structure.
However, in analogous art, Im discloses a flexible interconnect structure (Im: semiconductor device 10, Fig. 1E; said semiconductor device 10 showcases the entirety of the bridge/interconnection structure, with semiconductor chips 110 being analogous to the instant application’s first and second bridge die and interconnection 165 being analogous to the instant application’s flexible substrate).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the package structure as disclosed by Park such that the interconnect structure was flexible as disclosed by Im. One would be motivated to do so because the use of a flexible interconnect allows for the two interposers/dies to be connected to one another while being disposed on a non-flat surface (e.g., the dies can be at uneven/different heights) which increases device reliability in wearable devices (Im: [0054]).
Regarding Claim 13, Park/Im discloses the package structure as claimed in claim 12, wherein in a sectional view, a length of the flexible interconnect structure is larger than a total length of the first depression and the second depression (Park: Figs. 1 and 17; the length of the first depression is A2, and the length of the second depression is A2; however, the connection chip is double the length of A2 plus the space between the two interposers which would make the connection chip have a length larger than the total length of the two depressions).
Regarding Claim 14, Park/Im discloses the package structure as claimed in claim 12, wherein the flexible interconnect structure comprises:
a first bridge die (Im: semiconductor chip 110, see Annotated Fig. 1A);
a second bridge die (Im: semiconductor chip 110, see Annotated Fig. 1A);
a flexible substrate, wherein the first bridge die and the second bridge die are respectively adjacent to opposite ends of the flexible substrate (Im: interconnection 165, [0019], Fig. 1A);
a plurality of conductive lines disposed on the flexible substrate and electrically connecting the first bridge die to the second bridge die (Im: redistribution lines 130, [0023], Fig. 1A); and
a plurality of conductive bumps (Im: external terminals 150, [0024], Fig. 1A; Park: third chip pads 320, [0055]), wherein the first bridge die and the second bridge die are respectively bonded to the first package and the second package through the plurality of conductive bumps (Park: Fig. 2).
Claim(s) 5-6 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park/Im as applied to claims 1-4, 7, and 12-14 above, and further in view of Kang, et al. (US 2024/0079285 A1; hereinafter referred to as Kang).
Regarding Claim 5, Park/Im discloses the package structure as claimed in claim 4.
The combination of Park/Im fails to explicitly disclose that the package structure further comprises, a first encapsulant disposed on the first interposer and comprising: a first portion laterally encapsulating the first semiconductor die; and a second portion connected to the first portion and located between the flexible interconnect structure and the first interposer, wherein the plurality of first conductors penetrate through the second portion to electrically connect the flexible interconnect structure; and a second encapsulant disposed on the second interposer and comprising: a third portion laterally encapsulating the second semiconductor die; and a fourth portion connected to the third portion and located between the flexible interconnect structure and the second interposer, wherein the plurality of second conductors penetrate through the fourth portion to electrically connect the flexible interconnect structure.
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However, in analogous art, Kang discloses a package structure further comprising:
a first encapsulant disposed on the first interposer (Kang: molding layer 500, [0033], Fig. 1) and comprising:
a first portion laterally encapsulating the first semiconductor die (Kang: see Annotated Fig. 1); and
a second portion connected to the first portion and located between the flexible interconnect structure and the first interposer, wherein the plurality of first conductors penetrate through the second portion to electrically connect the flexible interconnect structure (Kang: see Annotated Fig. 1); and
a second encapsulant disposed on the second interposer and comprising (Kang: molding layer 500, [0033], Figs. 1 and 2; the disclosed structure repeats itself and, therefore, a second encapsulant would be present, as shown in Fig. 2, but is not depicted in Fig. 1):
a third portion laterally encapsulating the second semiconductor die (Kang: see Annotated Fig. 1); and
a fourth portion connected to the third portion and located between the flexible interconnect structure and the second interposer, wherein the plurality of second conductors penetrate through the fourth portion to electrically connect the flexible interconnect structure (Kang: see Annotated Fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the package structure as disclosed by Park/Im such that an encapsulation structure was present, as disclosed by Kang. One would be motivated to do so as the encapsulant being present between the bridge die/interconnection structure and the interposer/substrate can prevent warpage of the interposer/substrate and, therefore, the device in total will have increased structural stability (Kang: [0036]).
Regarding Claim 6, Park/Im/Kang discloses the package structure as claimed in claim 5, wherein:
the second portion is thinner than the first portion (Kang: see Annotated Fig. 1),
the fourth portion is thinner than the third portion (Kang: see Annotated Fig. 1).
Park/Im fail to explicitly disclose that the plurality of first and second conductors are thicker than the plurality of first and second bonding pads.
However, in analogous art, Kang discloses that the conductors located in the first and third portion of the encapsulant are thicker than the bonding pads corresponding to the first and second semiconductor dies (Kang: Figs. 1, 3).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the plurality of first and second conductors of Park/Im such that they are thicker than the plurality of first and second bonding pads, as disclosed by Kang. It would have been prima facie obvious because there is a clear finding that the prior art included each element and that one of ordinary skill in the art could have combined the teachings of Kang with Park/Im as it is known differing thicknesses of connectors will perform the same function of providing a sufficient electrical connection between interposer and die, and that one of ordinary skill in the art would have recognized this would lead to the predictable result of a functioning bridge die/interconnect. See MPEP 2143(I)(A).
Regarding Claim 16, Park/Im discloses the package structure as claimed in claim 12, wherein:
the first package comprises:
a first interposer bonded to the substrate (Park: interposer 200a, [0023], Fig. 2);
a first semiconductor die bonded to the first interposer (Park: chip 250a, [0023], Fig. 2); and
the second package comprises:
a second interposer bonded to the substrate (Park: interposer 200b, [0023], Fig. 2);
a second semiconductor die bonded to the second interposer (Park: chip 250b, [0023], Fig. 2).
The combination of Park/Im fails to explicitly disclose a first encapsulant disposed on the first interposer and laterally encapsulating the first semiconductor die, wherein in a sectional view, the first depression is on a side of the first encapsulant adjacent to the second package, and a second encapsulant disposed on the second interposer and laterally encapsulating the second semiconductor die, wherein in the sectional view, the second depression is on a side of the second encapsulant adjacent to the first package.
However, in analogous art, Kang discloses a package structure comprising:
a first encapsulant disposed on the first interposer and laterally encapsulating the first semiconductor die, wherein in a sectional view, the first depression is on a side of the first encapsulant adjacent to the second package (Kang: molding layer 500, [0033], Fig. 1),
a second encapsulant disposed on the second interposer and laterally encapsulating the second semiconductor die, wherein in the sectional view, the second depression is on a side of the second encapsulant adjacent to the first package (Kang: molding layer 500, [0033], Figs. 1 and 2; the disclosed structure repeats itself in Kang and, therefore, a second encapsulant would be present, as shown in Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the package structure as disclosed by Park/Im such that an encapsulation structure was present, as disclosed by Kang. One would be motivated to do so as the encapsulant being present between the bridge die/interconnection structure and the interposer/ substrate can prevent warpage of the interposer/substrate and, therefore, the device in total will have increased structural stability (Kang: [0036]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park/Im as applied to claims 1-4, 7, and 12-14 above, and further in view of Ecton, et al. (US 2025/0300086 A1; hereinafter referred to as Ecton).
Regarding Claim 8, Park/Im discloses the package structure as claimed in claim 7, wherein:
the plurality of conductive lines are located between the plurality of conductive bumps and the flexible substrate (Im: Fig. 1A).
The combination of Park/Im fails to explicitly disclose the flexible interconnect structure further comprises a plurality of through vias penetrating through the flexible substrate and electrically connecting the plurality of conductive lines to the first bridge die and the second bridge die.
However, in analogous art, Ecton discloses the flexible interconnect structure (Ecton: multi-die interconnect bridge 110, [0016-0017], Fig. 1) further comprises a plurality of through vias penetrating through the flexible substrate and electrically connecting the plurality of conductive lines to the first bridge die and the second bridge die (through-silicon vias 119, [0016], Fig. 1; the flexible substrate is made of glass as stated in [0016-0017], analogous to the instant application’s flexible substrate).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the flexible interconnect structure of Park/Im to include through-vias as disclosed by Ecton. One would be motivated to do so in order to route power and/or electrical signals to, from and/or between the interconnect structure and electrically connect all of the dies (Ecton: [0016]).
Claim(s) 10 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park/Im as applied to claims 1-4, 7, and 12-14 above, and further in view of Yang, et al. (US 2025/0132291 A1; hereinafter referred to as Yang).
Regarding Claim 10, Park/Im discloses the package structure as claimed in claim 7.
The combination of Park/Im fails to explicitly disclose wherein at least one of the first bridge die and the second bridge die comprises an embedded capacitor.
However, in analogous art, Yang discloses wherein at least one of the first bridge die and the second bridge die comprises an embedded capacitor (Yang: [0016]; “bridge die 104 may also contain IPDs, such as inductors, capacitors, and resistors”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the first or second bridge die of Park/Im such that it comprised an embedded capacitor, as disclosed by Yang. One would be motivated to do so as the inclusion of an embedded capacitor allows for RF signal processing to occur at the interconnection level (Yang: [0016]).
Regarding Claim 15, Park/Im discloses the package structure as claimed in claim 14.
The combination of Park/Im fails to explicitly disclose wherein at least one of the first bridge die and the second bridge die comprises an embedded capacitor.
However, in analogous art, Yang discloses wherein at least one of the first bridge die and the second bridge die comprises an embedded capacitor (Yang: [0016]; “bridge die 104 may also contain IPDs, such as inductors, capacitors, and resistors”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the first or second bridge die of Park/Im such that it comprised an embedded capacitor, as disclosed by Yang. One would be motivated to do so as the inclusion of an embedded capacitor allows for RF signal processing to occur at the interconnection level (Yang: [0016]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park/Im as applied to claims 1-4, 7, and 12-14 above, and further in view of Chen, et al. (US 2022/0415867 A1; hereinafter referred to as Chen) and further in view of Yim, et al. (US 2024/0395720 A1; hereinafter referred to as Yim).
Regarding Claim 11, Park/Im discloses the package structure as claimed in claim 1.
The combination of Park/Im fails to explicitly disclose the package structure further comprising: a third semiconductor die bonded to the first interposer and adjacent to the first semiconductor die.
However, in analogous art, Chen discloses a package structure further comprising:
a third semiconductor die (Chen: third semiconductor device die 104c, [0056], Fig. 10) bonded to the first interposer (Chen: interposer 108b, [0062], Fig. 10) and adjacent to the first semiconductor die (Chen: Fig. 10).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the package structure as disclosed by Park/Im such that a third semiconductor die is present and bonded to the first interposer along with the first semiconductor die, as disclosed by Chen. One would be motivated to add an additional die to the same interposer structure in order to provide high-speed high-bandwidth interconnections to and from the semiconductor dies and the package substrate (Chen: [0071]).
The combination of Park/Im/Chen further fails to disclose another flexible interconnect structure bonded to the first semiconductor die and the third semiconductor die, wherein the first semiconductor die and the third semiconductor die are located between the another flexible interconnect structure and the first interposer.
However, in analogous art, Yim discloses another flexible interconnect structure (Yang: bridge die 195, [0036], Fig. 1) bonded to the first semiconductor die (Yim: first semiconductor die 130, [0036], Fig. 1) and the third semiconductor die (Yim: second semiconductor die 140, [0036], Fig. 1) are located between the another flexible interconnect structure and the first interposer (Yim: Fig. 1; the bridge die is located above the two dies, and redistribution layer structure 110 is analogous to an interposer which is located below the two dies.)
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the package structure as disclosed by Park/Im/Chen such that an additional bridge die is bonded to the first and third semiconductor die as disclosed by Yim. One would be motivated to do so in order to electrically connect the first and third bridge dies (Yim: [0058]).
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park, further in view of Kang, and further in view of Im.
Regarding Claim 17, Park discloses a manufacturing method of a package structure (semiconductor package 10, [0023], Fig. 2), comprising:
bonding a first package to a substrate (first package, [0135], see Annotated Fig. 15);
bonding a second package to the substrate (second package, [0135], see Annotated Fig. 15);
patterning the first package to form a first depression that reveals at least one first conductor;
patterning the second package to form a second depression that reveals at least one second conductor; and
bonding an interconnect structure to the at least one first conductor and the at least one second conductor (connection chip 300, [0140], Fig. 17).
Park fails to explicitly disclose patterning the first and second package to form a first and second depression, respectively, that reveals at least one first and second conductor.
However, in analogous art, Kang discloses a first package structure being patterned to form a first depression which reveals at least one first conductor ([0073-0076], Figs. 7-9). As such, this process would be repeated to then pattern the second package to form a second depression.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the method of forming a package structure as disclosed by Park such that the first and second packages are patterned to form the depression rather than the depression being already present, as disclosed by Kang. One would be motivated to pattern the packages in such a way so as to have greater control of the encapsulant formation such that it covers the interposer/substrate under below which the interconnection chip will reside, thus protecting the interposer/substrate from warpage and increasing structural stability (Kang: [0076]).
The combination of Park/Kang fails to explicitly disclose that the interconnect structure can be a flexible interconnect structure.
However, in analogous art, Im discloses a flexible interconnect structure (Im: semiconductor device 10, Fig. 1E; said semiconductor device 10 showcases the entirety of the bridge/interconnection structure, with semiconductor chips 110 being analogous to the instant application’s first and second bridge die and interconnection 165 being analogous to the instant application’s flexible substrate).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the package structure as disclosed by Park/Kang such that the interconnect structure was flexible as disclosed by Im. One would be motivated to do so because the use of a flexible interconnect allows for the two interposers/dies to be connected to one another while being disposed on a non-flat surface (e.g., the dies can be at uneven/different heights) which increases device reliability in wearable devices (Im: [0054]).
Regarding Claim 18, Park/Kang/Im discloses the manufacturing method of the package structure as claimed in claim 17, wherein bonding the first package to the substrate comprises:
bonding a first interposer to the substrate (Park: interposer 200a, [0129], Fig. 13);
bonding a first semiconductor die to the first interposer (Park: chip 250a, [0135], Fig. 15); and
encapsulating the first semiconductor die and the at least one first conductor (Kang: mold M, [0074], Fig. 9).
Regarding Claim 19, Park/Kang/Im discloses the manufacturing method of the package structure as claimed in claim 17, wherein bonding the second package to the substrate comprises:
bonding a second interposer to the substrate (Park: interposer 200b, [0129], Fig. 13);
bonding a second semiconductor die to the second interposer (Park: chip 250a, [0135], Fig. 15); and
encapsulating the second semiconductor die and the at least one second conductor (Kang: mold M, [0074], Fig. 9).
Regarding Claim 20, Park/Kang/Im discloses the manufacturing method of the package structure as claimed in claim 17, wherein bonding the flexible interconnect structure to the at least one first conductor and the at least one second conductor comprises:
bonding a first bridge die and a second bridge die respectively to the at least one first conductor and the at least one second conductor through a plurality of conductive bumps (Park: third solder bump 270c, [0055], Fig. 17; Im: Fig. 1A), wherein a flexible substrate (Im: interconnection 165, Fig. 1A) on which a plurality of conductive lines electrically connected to the first bridge die and the second bridge die are disposed (Im: redistribution lines 130, Fig. 1A) is connected between the first bridge die and the second bridge die (Im: Fig. 1A).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(a) Marimuthu, et al. (US 2017/0271241 A1); discloses a fan-out package structure with a vertical interconnection
(b) Fang (US 2021/0043604 A1); discloses a package structure and manufacturing method
(c) Jeong, et al. (US 2018/0090449 A1); discloses IC package structure with interconnect
(d) Shim (US 2025/0062172 A1); discloses a semiconductor package with an encapsulant around only one chip/package
(e) Zingher, et al. (US 2010/0129999 A1); discloses a flexible bridge structure
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noah C. Robertson whose telephone number is (571) 317-0595. The examiner can normally be reached Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/Noah C. Robertson/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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