DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 4 in the reply filed on 07/24/2026 is acknowledged.
Claims 3-7, 12, 14-17 and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/24/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-2 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al, CN 219577258 U (Zhang ‘258) in view of Zhang et al, CN 115752878 A (Zhang ‘878).
Regarding claim 1; Zhang ‘258 teaches an electronic device, comprising:
a substrate (Zhang ‘258: Fig (5): Substrate), having a first upper surface (Upper Surface) and a lower surface (Lower Surface) opposite to each other,
a through hole (201) penetrating the substrate (Substrate) and connecting the upper surface (Upper Surface) and the lower surface (Lower Surface), and
a recess extending from the upper surface to the lower surface;
a package component (800), disposed on the upper surface (Upper Surface) of the substrate (Substrate), the package component (800) and the substrate(Substrate) defining a first chamber (First Chamber);
a spacer layer, disposed on the upper surface of the substrate and covering the recess, the spacer layer and the recess defining a second chamber;
a first sensor chip (500), disposed on the upper surface (Upper Surface) of the substrate (Substrate), located in the first chamber (First Chamber), and covering the through hole (201), wherein the first sensor chip (500) is electrically connected to a first processing chip (600);
a second processing chip, disposed in the recess of the substrate and located in the second chamber, wherein the second processing chip is air isolated from the first chamber; and
a gel, filling the second chamber and at least covering the second processing chip.
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Zhang ‘258 does not teach a recess extending from the upper surface to the lower surface; a spacer layer, disposed on the upper surface of the substrate and covering the recess, the spacer layer and the recess defining a second chamber; a second processing chip, disposed in the recess of the substrate and located in the second chamber, wherein the second processing chip is air isolated from the first chamber; a gel, filling the second chamber and at least covering the second processing chip.
Zhang ‘878 teaches a recess (Zhang ‘878: Annotated Fig (4) shared in this OA: Recess) extending from the upper surface (Upper Surface) to the lower surface (Lower Surface); a spacer layer (22), disposed on the upper surface (Upper Surface) of the substrate (21) and covering the recess (Recess), the spacer layer (22) and the recess (Recess) defining a second chamber (Second Chamber); a second processing chip (23, while Zhang ‘878 does not explicitly label 23 a processing chip, the significance of shielding it for protection applies in this case), disposed in the recess (Recess) of the substrate (21) and located in the second chamber (Second Chamber), wherein the second processing chip (23) is air isolated (the examiner is interpreting the language used to define this limitation as there is air isolating the second processing chip 23 from the first chamber ) from the first chamber (Fig (3): 10; additionally it is worth noting that Fig (4) is an enlarged and detailed depiction of feature 2 of Fig (3)); and a gel (Annotated Fig (4) shared in this OA: 24), filling the second chamber (Second Chamber) and at least covering the second processing chip (23).
Zhang ‘258 and Zhang ‘878 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Zhang ‘258 by constructing the recess disclosed in Zhang ‘878 to facilitate shielding the processing chip leading to a more reliable device.
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Regarding claim 2; Zhang ‘258 in view of Zhang ‘878 teaches all the limitations of the electronic device according to claim 1
Further, Zhang ‘258 teaches wherein the first processing chip (Zhang ‘258: Annotated Fig (5) shared in this OA: 600) is disposed on the upper surface (Upper Surface) of the substrate (Substrate) and adjacent to the first sensor chip (500) and located in the first chamber (First Chamber).
Regarding claim 18; Zhang ‘258 in view of Zhang ‘878 teaches all the limitations of the electronic device according to claim 1.
However, Zhang ‘258 does not teach further comprising: a plurality of bonding components, disposed between the spacer layer and the upper surface of the substrate, wherein the spacer layer is bonded to the substrate through the bonding components and is electrically connected to the substrate.
Zhang ‘878 teaches further comprising: a plurality of bonding components(Zhang ‘878: Annotated Fig (4) shared in this OA: 27), disposed between the spacer layer (22) and the upper surface (Upper Surface) of the substrate (21), wherein the spacer layer (22) is bonded to the substrate (21) through the bonding components (27) and is electrically connected (Page:-- Lines: -- of the translation of Zhang ‘878 attached to this OA: “… the sealing material 27 is tin paste or silver paste or glue, the metal supporting shell 21 surface is plated with nickel or gold…”; given the metallic nature of the bonding components 27, they will electrically connect the substrate 21 and the spacer layer 22) to the substrate (21).
Zhang ‘258 and Zhang ‘878 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Zhang ‘258 by bonding a spacer layer to the substrate using bonding components as disclosed in Zhang ‘878 to strengthen the structure of the device leading to a more reliable device.
Claims 8, 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al, CN 219577258 U (Zhang ‘258) in view of Zhang et al, CN 115752878 A (Zhang ‘878) in further view of Wang et al, CN 105990390 A (Wang).
Regarding claim 8; Zhang ‘258 in view of Zhang ‘878 teaches all the limitations of the electronic device according to claim 1.
Zhang ‘258 in view of Zhang ‘878 does not teach wherein the spacer layer comprises a first portion having a first thickness and a second portion having a second thickness, and the first thickness is less than the second thickness.
Wang teaches wherein the spacer layer (Wang: Annotated Fig (1) shared in this OA: 26) comprises a first portion (First Portion) having a first thickness (T1) and a second portion (Second Portion) having a second thickness (T2), and the first thickness (T1) is less than the second thickness (T2).
Zhang ‘258 in view of Zhang ‘878 and Wang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Zhang ‘258 in view of Zhang ‘878 by constructing a spacer layer with two different thicknesses as disclosed in Wang to fit into the recess and help create it in a level manner leading to better use of the space on the chip leading to a an increase of the number of chips in the package which in turn leads to a better performing device.
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Regarding claim 11; Zhang ‘258 in view of Zhang ‘878 teaches all the limitations of the electronic device according to claim 8.
However, Zhang ‘258 in view of Zhang 878 does not teach wherein the first portion and the second portion jointly define that the spacer layer is in a stepped shape.
Wang teaches wherein the first portion (Wang: Annotated Fig (1) shared in this OA: First Portion) and the second portion (Second Portion) jointly define that the spacer layer (26) is in a stepped shape.
Zhang ‘258 in view of Zhang ‘878 and Wang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to modify Zhang ‘258 in view of Zhang ‘878 by constructing the spacer layer as disclosed in Wang to create a space for isolating some of the processing chips to lower interference and thus improve the performance and reliability of the device.
Regarding claim 13; Zhang ‘258 in view of Zhang ‘878 teaches all the limitations of the electronic device according to claim 8.
However, Zhang ‘258 in view of Zhang ‘878 does not teach wherein the second portion further has an opening, and the gel completely fills the second chamber and covers the opening.
Wang teaches wherein the second portion (Wang: Annotated Fig (1) shared in this OA: Second Portion) further has an opening (Opening), and the gel (22) completely fills the second chamber (Second chamber) and covers the opening (Opening).
Zhang ‘258 in view of Zhang ‘878 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Zhang ‘258 in view of Zhang ‘878 by using a gel to fill the second chamber completely as disclosed in Wang to improve the isolation of the chips in the second chamber leading to a better performing device.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al, CN 219577258 U (Zhang ‘258) in view of Zhang et al, CN 115752878 A (Zhang ‘878) in further view of Wang et al, CN 105990390 A (Wang) in further view of Lee et al, US 20200132630 A1 (Lee).
Regarding claim 9; Zhang ‘258 in view of Zhang ‘878 in view of Wang teaches all the limitations of the electronic device according to claim 8.
Zhang ‘258 in view of Zhang ‘878 in view of Wang does not teach wherein the first processing chip is disposed on the first portion of the spacer layer and adjacent to the first sensor chip and located in the first chamber, and the first sensor chip is electrically connected to the substrate through the spacer layer.
Lee discloses wherein the first processing chip (Lee: Annotated Fig (6) shared in this OA: 120a) is disposed on the first portion of the spacer layer (200) and adjacent to the first sensor chip (110a) and located in the first chamber (First Chamber), and the first sensor chip (110a) is electrically connected to the substrate (300) through the spacer layer (200).
Zhang ‘258 in view of Zhang ‘878 in further view of Wang and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Zhang ‘258 in view of Zhang ‘878 in further view of Wang by placing the first processing chip and the first sensor chip on the spacer layer to improve the isolation of the sensor from other noise sources leading to a more reliable device.
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Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al, CN 219577258 U (Zhang ‘258) in view of Zhang et al, CN 115752878 A (Zhang ‘878) in further view of Wang et al, CN 105990390 A (Wang) in further view of Lee et al, US 20200132630 A1 (Lee) in further view of Ma et al, US 20130249109 A1 (Ma).
Regarding claim 10; Zhang ‘258 in view of Zhang ‘878 in further view of Wang in further view of Lee teaches all the limitations of the electronic device according to claim 9.
Zhang ‘258 in view of Zhang ‘878 in further view of Wang in further view of Lee does not teach further comprising: a second sensor chip, disposed on the second portion of the spacer layer and located in the first chamber, wherein a portion of the second sensor chip is stacked on the first processing chip, and the second sensor chip is electrically connected to the second processing chip through the substrate.
Ma teaches further comprising: a second sensor chip (Ma: Fig (2): 208B), disposed on the second portion of the spacer layer (202) and located in the first chamber (top portion of the device), wherein a portion of the second sensor chip (208B) is stacked on the first processing chip (205B), and the second sensor chip (208B) is electrically connected to the second processing chip (205A) through the substrate (201+203; see the connection pads 22A).
Zhang ‘258 in view of Zhang ‘878 in further view of Wang in further view of Lee and Ma are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Zhang ‘258 in view of Zhang ‘878 in further view of Wang in further view of Lee by depositing the second sensor chip as disclosed in Ma to enhance the isolation of the sensor chip from the processing chip while improving the ability of the sensor to perform measurements leading to a better performing device.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al, CN 219577258 U (Zhang ‘258) in view of Zhang et al, CN 115752878 A (Zhang ‘878) in further view of Lin et al, CN 110164861 A (Lin)
Regarding claim 20; Zhang ‘258 in view of Zhang ‘878 teaches all the limitations of the electronic device according to claim 1.
Zhang ‘258 in view of Zhang ‘878 does not teach further comprising: a plurality of conductive components, disposed on the lower surface of the substrate and electrically connected to the first processing chip and the second processing chip.
Lin teaches further comprising: a plurality of conductive components (Lin: Fig (35F): 99), disposed on the lower surface of the substrate (101) and electrically connected to the first processing chip (317) and the second processing chip (100).
Zhang ‘258 in view of Zhang ‘878 and Lin are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Zhang’ 285 in view of Zhang ‘878 by constructing the conductive components on the lower surface of the substrate as disclosed in Lin to make establishing electrical connections within the device easier leading to a more reliable and efficient device manufacturing process.
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Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Liu et al, US 20250379199 A1 (Liu); discloses a chip package with multiple chambers and a multitude of chips in each of the chambers. It also discloses a gel covering one of the chips.
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/M.K./Examiner, Art Unit 2817
/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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