DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group II, claims 10-20, in the reply filed on 7/22/26 is acknowledged.
Claims 1-9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/22/26.
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-16, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pritchard et al., US 10651136 B2 in view of Pellela, US 7718503 B2.
Pritchard teaches:
10. A manufacturing method of a semiconductor structure, comprising (see figs. 1-2):
providing a substrate (e.g. substrate at col 6, ln 30–53), wherein the substrate has an active area (e.g. region of transistor 150) and a dummy area (e.g. region of discharge structure 120);
forming an active component (150) in the active area of the substrate;
forming at least one discharge structure (120) in the dummy area of the substrate;
forming a fuse (130) connected to the at least one discharge structure;
forming an interconnection metal layer (110/111/112/152) over the active component (150), the at least one discharge structure (120), and the fuse (130); and
Pritchard does not expressly teach a multi-layer interconnection and
forming a gate pad over the multi-layer interconnection metal layer, wherein the gate pad is electrically connected to the active component and the fuse through the multi-layer interconnection metal layer.
In an analogous art, Pallela teaches:
forming a multi-layer interconnection metal layer (402/100/102/406) over the active component (64), the at least one discharge structure (177),…and
forming a gate pad (410) over the multi-layer interconnection metal layer, wherein the gate pad (410) is electrically connected to the active component (64) [and the discharge structure (177)] through the multi-layer interconnection metal layer (402/100/102/406). (e.g. See “… although not illustrated in the figures, the discharge path can also extend from a gate electrode such as gate electrode 302 of MOS transistor 300 to the pn junction diode.”, col 11, ln 41–67)
One of ordinary skill in the art modifying Pritchard with Pallela to form a multi-layer interconnection and a forming a gate pad over the multi-layer interconnection would form “wherein the gate pad is electrically connected to the active component and the fuse through the multi-layer interconnection metal layer” because Pritchard’s fuse is disposed between the active component and the discharge structure.
Regarding claim 11:
Pritchard further teaches:
11. The manufacturing method of the semiconductor structure of claim 10, further comprising: providing a bias voltage to the fuse to blow the fuse (e.g. “…enabling the “blowing” of the fuse structure upon applying an appropriate stimulus, such as an electrical current, heat, radiation and the like., col 6, ln 53–67, col 7, ln 2-25.)
Regarding claims 12-13:
Pallela further teaches:
12. The manufacturing method of the semiconductor structure of claim 10, wherein the at least one discharge structure (177) is formed in the substrate (34), fig. 11.
13. The manufacturing method of the semiconductor structure of claim 12, wherein a top surface of the at least one discharge structure (177) is leveled with a surface of the substrate (34), fig. 11.
Regarding claim 14:
Pallela further teaches:
14. The manufacturing method of the semiconductor structure of claim 10, wherein the at least one discharge structure (177) comprises a metal conductive material (e.g. silicide 178), col 6, ln 55–67, col 7, ln 1–15.
It is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
Regarding claim 15:
Pritchard further teaches:
15. The manufacturing method of the semiconductor structure of claim 10, wherein a number of the at least one discharge structure (120, 220) is plural, and the discharge structures are arranged at an interval on the substrate, figs. 1A, 2A.
Pritchard does not expressly teach:
the discharge structures are arranged in an orthographic projection of the gate pad on the substrate.
Pellela further teaches
the discharge structure (177) is arranged in an orthographic projection of the gate pad (140) on the substrate, fig. 11.
Regarding claim 16:
Pritchard further teaches:
16. The manufacturing method of the semiconductor structure of claim 10, a number of the at least one discharge structure (120, 220) is plural, and the discharge structures are arranged in an array (e.g. see fig. 1A and 3x1 array in fig. 2A).
Regarding claim 18:
Pritchard further teaches:
18. The manufacturing method of the semiconductor structure of claim 10, wherein the fuse (130) is formed on the substrate.
Regarding claim 20:
Pritchard further teaches:
20. The manufacturing method of the semiconductor structure of claim 10, wherein the forming a multi-layer interconnection metal layer comprises performing a plasma process, and charges in the plasma process is conducted out of the substrate through the fuse and the at least one discharge structure, col 2, ln 15–55, col 14-17, ln 1– 67.
Pallela also teaches:
20. The manufacturing method of the semiconductor structure of claim 10, wherein the forming a multi-layer interconnection metal layer comprises performing a plasma process, and charges in the plasma process is conducted out of the substrate through the fuse and the at least one discharge structure, col 1, ln 55–67, col 8, ln 41–59.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Pritchard with the teachings of Pellela to provide a discharge path to address the problem of “The charge build up results from one or more of the plasma deposition and/or etching steps that are used to deposit and/or etch the interlayer dielectric materials and the metals or other conductors used in the final steps in fabricating the integrated circuits.” See Pallela at Abstract and col 1, ln 55–67.
Claim(s) 12, 13 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pritchard in view of Pellela, as applied to claim 10 above, in further view of Tsai et al., US 20220406608 A1.
Regarding claims 12-13:
Pritchard and Pellela teach all the limitations of claim 10 above, and in an alternative interpretation of claims 12-13, the reference Tsai is being introduced.
In an analogous art, Tsai teaches:
12. The manufacturing method of the semiconductor structure of claim 10, wherein the at least one discharge structure (120/134/132) is formed in the substrate (100), fig. 19, para. [0059] – [0060].
13. The manufacturing method of the semiconductor structure of claim 12, wherein a top surface of the at least one discharge structure (120/134/132) is leveled with a surface of the substrate (100), fig. 19, para. [0059] – [0060].
Regarding claim 19:
Tsai further teaches:
19. The manufacturing method of the semiconductor structure of claim 10, further comprising: forming a well (110) in the substrate, wherein the at least one discharge structure (120/134/132) is formed in the well (110), fig. 19, para. [0059] – [0060].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Pritchard with the teachings of Tsai because “…the accumulating charges C1 can be drained from the DNW region 110 to the substrate 100 through the doped region 134…the accumulating charges C1 are directed toward the diode 130 instead of flowing through the gate dielectrics 12, 22,…to be protected from damage of plasma induced charges.” See Tsai at para. [0060].
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
23 September 2026
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