DETAILED ACTION
This Office Action is in response to an application that was filed on 04/26/2024. Claims 1-20 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
In independent claim 1, the limitation phrase “first build-up layer” in the limitation “wherein the first build-up layer is formed such that the first conductor layers and via conductors include a first layer and a second layer formed on the first layer”, is confusing. The premise of the confusion is compounded by the limitation phrase “first build-up layer” NOT having the proper antecedent basis. Therefore, the claim DOES NOT make it clear if the cited limitation structure “first build-up layer” is the limitation structure in the earlier limitation “first build-up part” OR the limitation structure “first build-up layer” in ¶[0004] of the specification with no item designation in the Drawings, OR entirely different “first build-up layer” limitation structure. The limitation “wherein the first build-up layer is formed such that the first conductor layers and via conductors include a first layer and a second layer formed on the first layer” will be examine as “wherein the first build-up part is formed such that the first conductor layers and via conductors include a first layer and a second layer formed on the first layer” to conform with the filed Drawings.
In independent claim 1, the limitation phrase “via conductors” in the limitation “wherein the first build-up part is formed such that the first conductor layers and via conductors include a first layer and a second layer formed on the first layer” (amended for examination), is confusing. The premise of the confusion is compounded by the limitation phrase “via conductors” NOT having the proper antecedent basis. Therefore, the claim DOES NOT make it clear if the cited limitation structure “via conductors” is the limitation structure in the earlier limitation “first via conductors” OR entirely different limitation structure in the “second or third build-up part”. The limitation “wherein the first build-up part is formed such that the first conductor layers and via conductors include a first layer and a second layer formed on the first layer” will be examine as “wherein the first build-up part is formed such that the first conductor layers and the first via conductors include a first layer and a second layer formed on the first layer”.
Claims 2-20 are rejected since the base independent claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
In claim 2, the limitation phrase “via conductors” in the limitation “wherein the first conductor layers and via conductors in the first build-up part is formed such that the element of the alloy in the lower layer of the first layer is silicon”, is confusing. Therefore, the claim DOES NOT make it clear if the cited limitation structure “via conductors” is the limitation structure in the limitation “first via conductors” in independent claim 1 OR entirely different limitation structure in the “second or third build-up part”.
Claims 3, 19-20 are rejected since the base claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
In claim 4, the limitation phrase “via conductors” in the limitation “wherein the first conductor layers and via conductors in the first build-up part is formed such that a content of the aluminum in the alloy in the lower layer of the first layer is 1.0 at % or more and 15.0 at % or less”, is confusing. Therefore, the claim DOES NOT make it clear if the cited limitation structure “via conductors” is the limitation structure in the limitation “first via conductors” in independent claim 1 OR entirely different limitation structure in the “second or third build-up part”.
In claim 5, the limitation phrase “via conductors” in the limitation “wherein the first conductor layers and via conductors in the first build-up part is formed such that the alloy in the lower layer of the first layer includes carbon”, is confusing. Therefore, the claim DOES NOT make it clear if the cited limitation structure “via conductors” is the limitation structure in the limitation “first via conductors” in independent claim 1 OR entirely different limitation structure in the “second or third build-up part”.
Claim 6 is rejected since the base claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
In claim 7, the limitation phrase “via conductors” in the limitation “wherein the first conductor layers and via conductors in the first build-up part is formed such that the alloy in the lower layer of the first layer includes oxygen”, is confusing. Therefore, the claim DOES NOT make it clear if the cited limitation structure “via conductors” is the limitation structure in the limitation “first via conductors” in independent claim 1 OR entirely different limitation structure in the “second or third build-up part”.
Claim 8 is rejected since the base claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
In claim 9, the limitation phrase “via conductors” in the limitation “wherein the first conductor layers and via conductors in the first build-up part is formed such that a content of the copper in the lower layer of the first layer is 90 at % or more”, is confusing. Therefore, the claim DOES NOT make it clear if the cited limitation structure “via conductors” is the limitation structure in the limitation “first via conductors” in independent claim 1 OR entirely different limitation structure in the “second or third build-up part”.
In claim 10, the limitation phrase “via conductors” in the limitation “wherein the first conductor layers and via conductors in the first build-up part is formed such that a content of the copper in the upper layer of the first layer is 99.9 at % or more”, is confusing. Therefore, the claim DOES NOT make it clear if the cited limitation structure “via conductors” is the limitation structure in the limitation “first via conductors” in independent claim 1 OR entirely different limitation structure in the “second or third build-up part”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 14, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi et al. (US20090072404A1 and Kikuchi hereinafter), in view of Zhong et al. (US20100163288A1 and Zhong hereinafter), and in further view of Zhang (US2022/0052207A1 and Zhang hereinafter).
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Reproduce Drawing of Fig. 2 from Kikuchi et al. (US20090072404A1)
Regarding claim 1, Kikuchi discloses a wiring substrate (item 12 of Fig. 2 & Reproduced Drawing and ¶[0040] shows and indicates wiring substrate 12 {first wiring structure 12}), comprising: a first build-up part comprising a plurality of first insulating layers, a plurality of first conductor layers, and a plurality of first via conductors (items 27, 26, 30 of Fig. 2 & items A, 27-A, 26-A, 30-A of Reproduced Drawing and ¶[0040] shows and indicates first build-up part A comprising the plurality of first insulating layers 27-A {insulating layers 27 of first build-up part A}, the plurality of first conductor layers 26-A {first wiring layers 26 of first build-up part A}, and the plurality of first via conductors 30-A {first via 30 of first build-up part A}); and a second build-up part laminated on the first build-up part and comprising a plurality of second insulating layers and a plurality of second conductor layers such that a minimum wiring width of wirings in the first conductor layers is smaller than a minimum wiring width of wirings in the second conductor layers and that a minimum inter-wiring distance of the wirings in the first conductor layers is smaller than a minimum inter-wiring distance of the wirings in the second conductor layers (Fig. 2 & items B, 27-B, 26-B of Reproduced Drawing and ¶[0040] shows and indicates second build-up part B laminated on first build-up part A and comprised of the plurality of second insulating layers 27-B {insulating layers 27 of second build-up part B} and the plurality of second conductor layers 26-B {first wiring layers 26 of second build-up part B}; where Reproduced Drawing & Fig. 2 shows second conductor layers 26-B is such that the minimum wiring width of wirings in first conductor layers 26-A is smaller than the minimum wiring width of wirings in second conductor layers 26-B; and where Reproduced Drawing & Fig. 2 shows second conductor layers 26-B is such that the minimum inter-wiring distance of the wirings in first conductor layers 26-A is smaller than the minimum inter-wiring distance of the wirings in second conductor layers 26-B), wherein the first build-up part is formed such that the first conductor layers and first via conductors is comprised a sputtering films (item 28 of Fig. 2 & Reproduced Drawing and ¶[0040 & 0046-0047] shows and indicates where first build-up part A is formed such that first conductor layers 26-A and first via conductors 30-A is comprised the sputtering films {wiring 28 of the first wiring layers 26 of the first wiring structure 12 and first via 30 of the first wiring structure 12 are both mainly comprised of Cu or Al by way of the damascene method that provides a barrier metal by a sputtering method}).
Kikuchi discloses the claimed invention except wherein the first build-up part is formed such that the first conductor layers and first via conductors include a first layer and a second layer formed on the first layer, the first layer includes a lower layer comprising a sputtering film comprising an alloy comprising copper, aluminum, and at least one element selected from group consisting of nickel, zinc, gallium, silicon, and magnesium, and an upper layer comprising a sputtering film comprising copper, and the lower layer is formed in contact with surfaces of the first insulating layers and inner wall surfaces and bottom surfaces in via openings for the first via conductors.
Zhong disclose wherein the first build-up part is formed such that the first conductor layers and first via conductors include a first layer and a second layer formed on the first layer, the first layer includes a lower layer comprising a sputtering film comprising copper, and an upper layer comprising a sputtering film comprising copper, and the lower layer is formed in contact with surfaces of the first insulating layers and inner wall surfaces and bottom surfaces in via openings for the first via conductors (items 5, 11, 7 of Fig. 4(a) & items 12, 13 of Fig. 3(c) & item 2 of Figs. 3(c)-4(b) and ¶[0049_0200_ 0387_0392-0393_0396-0397_0414-0415 & 0424] shows and indicates where first build-up part of Fig. 4(a) {multilayered printed circuit board of Fig. 4(a), indicated in ¶[0049 & 0387]} is formed such that first conductor layers 5_11 {conducting structure formed by conductor circuits 5 that is interpreted to comprise of the copper films 12 and the copper films 13, indicated in ¶[0200_0396-0397 & 0424], and thick roughened alloy layers 11 composed of Cu—Ni—P surrounding conductor circuits 5, indicated in ¶[0397]} and first via conductors 7 {via-holes, indicated in ¶[0396]} include first layer 5 and second layer 11 formed on first layer 5; where first layer 5 includes lower layer 12 {interpreted to indicate sputtering copper films 12, indicated in ¶[0200 & 0392]} comprising a sputtering film comprising copper; and where upper layer 13 {interpreted to indicate sputtering thick copper films 13, indicated in ¶[0200 & 0393]} comprising a sputtering film comprising copper; and where lower layer 12 is formed in contact with surfaces of first insulating layers 2 {interlaminar resin insulating layers 2, indicated in ¶[0414-0415]} and inner wall surfaces and bottom surfaces in via openings for the first via conductors 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the first build-up part is formed such that the first conductor layers and first via conductors include a first layer and a second layer formed on the first layer, the first layer includes a lower layer comprising a sputtering film comprising copper, and an upper layer comprising a sputtering film comprising copper, and the lower layer is formed in contact with surfaces of the first insulating layers and inner wall surfaces and bottom surfaces in via openings for the first via conductors into the device of Kikuchi. One would have been motivated in the wiring substrate of Kikuchi and have the first build-up part be formed such that the first conductor layers and first via conductors include the first layer and the second layer formed on the first layer, the first layer includes the lower layer comprising a sputtering film comprising copper, and the upper layer comprising a sputtering film comprising copper, and the lower layer is formed in contact with surfaces of the first insulating layers and inner wall surfaces and bottom surfaces in via openings for the first via conductors, in order to design a PCB with roughened surface conductor layer with the layer having uniform roughness to provide high adhesion strength to the metal layers of conductor circuitry to the resin layer/film, as indicated by Zhong in ¶[0167], in the wiring board of Kikuchi.
However, Kikuchi and Zhong do not disclose wherein the conductor layer include a layer, the layer includes a lower layer comprising a film comprising an alloy comprising copper, aluminum, and nickel, and an upper layer.
Zhang disclose wherein the conductor layer include a layer, the layer includes a lower layer comprising a film comprising an alloy comprising copper, aluminum, and nickel, and an upper layer (item 61 of Fig. 1 and ¶[0028] shows and indicates where conductor layer 61 {electrode 61} include a layer, the layer includes the lower layer {upper layer} comprising a film that comprises an alloy comprising copper, aluminum, and nickel {electrode 61 may be a multilayer structure that may include an upper layer including Al, Ni, and Cu or an alloy thereof}, and the upper layer {lower level; where electrode 61 may be a multilayer structure that may include a lower layer including Ti or TiN}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the conductor layer include a layer, the layer includes a lower layer comprising a film comprising an alloy comprising copper, aluminum, and nickel, and an upper layer into the device of modified Kikuchi. One would have been motivated in the wiring substrate of modified Kikuchi and have the conductor layer include a layer, the layer includes the lower layer comprising a film comprising an alloy comprising copper, aluminum, and nickel, and an upper layer, in order to design a PCB with a versatile alloy conductor structure and make allowances in the variation of a conductor layer that features a variety of environments (e.g., at different voltages and frequencies), as inferred by Zhang in ¶[0002 & 0028], in the wiring board of modified Kikuchi.
In addition, the applicant has not disclosed that selecting the conductor layer includes a lower layer comprising a film comprising an alloy comprising copper, aluminum, and at least one element selected from group consisting of nickel, zinc, gallium, silicon, and magnesium solves any stated problems or provides any unexpected results within the choice of materials in the conductor layer. As such, the Examiner considers this limitation to be a design choice. Therefore, it would have been obvious as matter of obvious design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to have the conductor layer be comprised of Cu-AL-Ni alloy, as indicated by Zhang, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
Regarding claim 14, modified Kikuchi discloses a wiring substrate, wherein the first build-up part is formed such that each of the first conductor layers has a polished surface on a second build-up part side (Kikuchi: item 28 of Fig. 2 & Reproduced Drawing and ¶[0040 & 0047] shows and indicates where first build-up part A is formed such that each first conductor layers 26-A has a polished surface on second build-up part B side {wiring 28 and first via 30 of the first wiring structure 12 mainly comprise Cu or Al will then apply a CMP [Chemical Mechanical Polishing] method which leaves the copper only in the trench that is formed by the damascene method, thereby providing the desired wiring}).
Regarding claim 15, modified Kikuchi discloses a wiring substrate, further comprising: a third build-up part formed on the second build-up part on an opposite side with respect to the first build-up part and comprising a third insulating layer and a third conductor layer (Kikuchi: items C, 27-C, 26-C of Reproduced Drawing & Fig. 2 and ¶[0040] shows and indicates that wiring substrate 12 is further comprised of third build-up part C formed on second build-up part B on an opposite side with respect to first build-up part A and comprising third insulating layer 27-C {insulating layers 27 of third build-up part C} and a third conductor layer 26-C {first wiring layers 26 of third build-up part C}).
Regarding claim 16, modified Kikuchi discloses a wiring substrate, wherein the third insulating layer includes a core material (Kikuchi: item 29 of Fig. 2 & Reproduced Drawing and ¶[0040 & 0046] shows and indicates where third insulating layer 27-C includes core material 29 {insulating film 29 composes first insulating layer 27}).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi in view of Zhong and Zhang, as detailed in the rejection of claim 1 above, and in further view of Niki (US20100116529A1 and Niki hereinafter).
Regarding claim 11, modified Kikuchi discloses a wiring substrate, wherein the first build-up part is formed such that the plurality of first insulating layers includes insulating resin and that the inner wall surfaces of the via openings include surfaces of the insulating resin and flat parts substantially flush with each other (Zhong: Figs. 3(c)-4(b) and ¶[0049_0200_ 0387_0392-0393_0396-0397_0414-0415 & 0424] shows and indicates where first build-up part of Fig. 4(a) is formed such that first insulating layers 2 includes insulating resin; Kikuchi: Fig. 2 & Reproduced Drawing and ¶[0040] shows where the plurality of first insulating layers 27-A; and where in first build-up part A is comprised of the inner wall surfaces of the via openings of first via conductors 30-A include surfaces of the insulating of first insulating layers 27-A that are flat parts substantially flush with each other).
However, Kikuchi, Zhong, and Zhang do not disclose wherein insulating layers includes insulating resin and inorganic particles.
Niki disclose wherein insulating layers includes insulating resin and inorganic particles (claim 12 indicates where insulating layers includes insulating resin and inorganic particles).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein insulating layers includes insulating resin and inorganic particles into the device of modified Kikuchi. One would have been motivated in the wiring substrate of modified Kikuchi and have the insulating layers include insulating resin and inorganic particles, in order to design a PCB with an increase strengthen substrate through the plurality of insulating layers, as indicated by Niki in ¶[0058], in the wiring board of modified Kikuchi.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi in view of Zhong and Zhang, as detailed in the rejection of claim 16 above, and in further view of Nakatani et al. (US20130200516A1 and Nakatani hereinafter).
Regarding claim 17, modified Kikuchi discloses a wiring substrate, wherein the core material (Kikuchi: Fig. 2 & Reproduced Drawing and ¶[0040 & 0046] shows and indicates core material 29).
However, Kikuchi, Zhong, and Zhang do not disclose wherein the core material includes a glass fiber.
Nakatani disclose wherein the core material includes a glass fiber (item 10 of Fig. 1 and ¶[0064-0065] shows and indicates where the core material of core layer 10 includes glass fiber).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the core material includes a glass fiber into the device of modified Kikuchi. One would have been motivated in the wiring substrate of modified Kikuchi and have the core material includes a glass fiber, in order to design a PCB with a reinforced base substrate, as indicated by Nakatani in ¶[0065], in the wiring board of modified Kikuchi.
Claims 1, 15, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US20200411442 A1 and Hu hereinafter), in view of Zhong, and in further view of Zhang.
Regarding claim 1, Hu discloses a wiring substrate (item 100 of Fig. 3B and ¶[0035] shows and indicates wiring substrate 100 {package substrate 100}), comprising: a first build-up part comprising a plurality of first insulating layers, a plurality of first conductor layers, and a plurality of first via conductors (items FRDC, FD, FP, FV of Fig. 1 and ¶[0023-0024] shows and indicates first build-up part FRDC {fine redistribution circuitry FRDC} comprising the plurality of first insulating layers FD { fine dielectric layer FD}, the plurality of first conductor layers FP { fine conductive pattern FP}, and the plurality of first via conductors FV {fine conductive via FV}); and a second build-up part laminated on the first build-up part and comprising a plurality of second insulating layers and a plurality of second conductor layers such that a minimum wiring width of wirings in the first conductor layers is smaller than a minimum wiring width of wirings in the second conductor layers and that a minimum inter-wiring distance of the wirings in the first conductor layers is smaller than a minimum inter-wiring distance of the wirings in the second conductor layers (items CRDC, CD, CP, BP of Fig. 1 and ¶[0023 & 0026] shows and indicates second build-up part CRDC {coarse redistribution circuitry CRDC} laminated on first build-up part FRDC and comprised of the plurality of second insulating layers CD {coarse dielectric layer CD} and the plurality of second conductor layers CP-BP {coarse conductive pattern CP and bonding pad BP}; where Fig. 1 shows second conductor layers CP-BP is such that the minimum wiring width of wirings in first conductor layers FP is smaller than the minimum wiring width of wirings in second conductor layers CP-BP; and where Fig. 1 shows second conductor layers BP portion of second conductor layers CP-BP is such that the minimum inter-wiring distance of the wirings in first conductor layers FP is smaller than the minimum inter-wiring distance of the wirings in second conductor layers BP portion of second conductor layers CP-BP).
Hu discloses the claimed invention except wherein the first build-up part is formed such that the first conductor layers and first via conductors include a first layer and a second layer formed on the first layer, the first layer includes a lower layer comprising a sputtering film comprising an alloy comprising copper, aluminum, and at least one element selected from group consisting of nickel, zinc, gallium, silicon, and magnesium, and an upper layer comprising a sputtering film comprising copper, and the lower layer is formed in contact with surfaces of the first insulating layers and inner wall surfaces and bottom surfaces in via openings for the first via conductors.
Zhong disclose wherein the first build-up part is formed such that the first conductor layers and first via conductors include a first layer and a second layer formed on the first layer, the first layer includes a lower layer comprising a sputtering film comprising copper, and an upper layer comprising a sputtering film comprising copper, and the lower layer is formed in contact with surfaces of the first insulating layers and inner wall surfaces and bottom surfaces in via openings for the first via conductors (items 5, 11, 7 of Fig. 4(a) & items 12, 13 of Fig. 3(c) & item 2 of Figs. 3(c)-4(b) and ¶[0049_0200_ 0387_0392-0393_0396-0397_0414-0415 & 0424] shows and indicates where first build-up part of Fig. 4(a) {multilayered printed circuit board of Fig. 4(a), indicated in ¶[0049 & 0387]} is formed such that first conductor layers 5_11 {conducting structure formed by conductor circuits 5 that is interpreted to comprise of the copper films 12 and the copper films 13, indicated in ¶[0200_0396-0397 & 0424], and thick roughened alloy layers 11 composed of Cu—Ni—P surrounding conductor circuits 5, indicated in ¶[0397]} and first via conductors 7 {via-holes, indicated in ¶[0396]} include first layer 5 and second layer 11 formed on first layer 5; where first layer 5 includes lower layer 12 {interpreted to indicate sputtering copper films 12, indicated in ¶[0200 & 0392]} comprising a sputtering film comprising copper; and where upper layer 13 {interpreted to indicate sputtering thick copper films 13, indicated in ¶[0200 & 0393]} comprising a sputtering film comprising copper; and where lower layer 12 is formed in contact with surfaces of first insulating layers 2 {interlaminar resin insulating layers 2, indicated in ¶[0414-0415]} and inner wall surfaces and bottom surfaces in via openings for the first via conductors 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the first build-up part is formed such that the first conductor layers and first via conductors include a first layer and a second layer formed on the first layer, the first layer includes a lower layer comprising a sputtering film comprising copper, and an upper layer comprising a sputtering film comprising copper, and the lower layer is formed in contact with surfaces of the first insulating layers and inner wall surfaces and bottom surfaces in via openings for the first via conductors into the device of Hu. One would have been motivated in the wiring substrate of Hu and have the first build-up part be formed such that the first conductor layers and first via conductors include the first layer and the second layer formed on the first layer, the first layer includes the lower layer comprising a sputtering film comprising copper, and the upper layer comprising a sputtering film comprising copper, and the lower layer is formed in contact with surfaces of the first insulating layers and inner wall surfaces and bottom surfaces in via openings for the first via conductors, in order to design a PCB with roughened surface conductor layer with the layer having uniform roughness to provide high adhesion strength to the metal layers of conductor circuitry to the resin layer/film, as indicated by Zhong in ¶[0167], in the wiring board of Hu.
However, Hu and Zhong do not disclose wherein the conductor layer include a layer, the layer includes a lower layer comprising a film comprising an alloy comprising copper, aluminum, and nickel, and an upper layer.
Zhang disclose wherein the conductor layer include a layer, the layer includes a lower layer comprising a film comprising an alloy comprising copper, aluminum, and nickel, and an upper layer (item 61 of Fig. 1 and ¶[0028] shows and indicates where conductor layer 61 {electrode 61} include a layer, the layer includes the lower layer {upper layer} comprising a film that comprises an alloy comprising copper, aluminum, and nickel {electrode 61 may be a multilayer structure that may include an upper layer including Al, Ni, and Cu or an alloy thereof}, and the upper layer {lower level; where electrode 61 may be a multilayer structure that may include a lower layer including Ti or TiN}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the conductor layer include a layer, the layer includes a lower layer comprising a film comprising an alloy comprising copper, aluminum, and nickel, and an upper layer into the device of modified Hu. One would have been motivated in the wiring substrate of modified Hu and have the conductor layer include a layer, the layer includes the lower layer comprising a film comprising an alloy comprising copper, aluminum, and nickel, and an upper layer, in order to design a PCB with a versatile alloy conductor structure and make allowances in the variation of a conductor layer that features a variety of environments (e.g., at different voltages and frequencies), as inferred by Zhang in ¶[0002 & 0028], in the wiring board of modified Hu.
In addition, the applicant has not disclosed that selecting the conductor layer includes a lower layer comprising a film comprising an alloy comprising copper, aluminum, and at least one element selected from group consisting of nickel, zinc, gallium, silicon, and magnesium solves any stated problems or provides any unexpected results within the choice of materials in the conductor layer. As such, the Examiner considers this limitation to be a design choice. Therefore, it would have been obvious as matter of obvious design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to have the conductor layer be comprised of Cu-AL-Ni alloy, as indicated by Zhang, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
Regarding claim 15, modified Hu discloses a wiring substrate, further comprising: a third build-up part formed on the second build-up part on an opposite side with respect to the first build-up part and comprising a third insulating layer and a third conductor layer (Hu: items 120, 124, 128 of Fig. 3A and ¶[0029-0030] shows and indicates that wiring substrate 100 is further comprised of third build-up part 120 {core 120} formed on second build-up part CRDC on an opposite side with respect to first build-up part FRDC and comprising third insulating layer 124 {core dielectric layer 124} and a third conductor layer 128 {second core pad 128}).
Regarding claim 16, modified Hu discloses a wiring substrate, wherein the third insulating layer includes a core material (Hu: Fig. 3A and ¶[0029-0030] shows and indicates where third insulating layer 124 includes core material of core dielectric).
Regarding claim 18, modified Hu discloses a wiring substrate, wherein the first build-up part is formed such that each of the first via conductors has a shape that is reduced in diameter away from the second build-up part (Hu: Fig. 1 and ¶[0023-0024 & 0026] shows where first build-up part FRDC is formed such that each of first via conductors FV has a shape that is reduced in diameter away from second build-up part CRDC).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hu in view of Zhong and Zhang, as detailed in the rejection of claim 16 above, and in further view of Nakatani.
Regarding claim 17, modified Hu discloses a wiring substrate, wherein the core material (Hu: Fig. 3A and ¶[0029-0030] shows and indicates where the core material is the core dielectric).
However, Hu, Zhong, and Zhang do not disclose wherein the core material includes a glass fiber.
Nakatani disclose wherein the core material includes a glass fiber (item 10 of Fig. 1 and ¶[0064-0065] shows and indicates where the core material of core layer 10 includes glass fiber).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the core material includes a glass fiber into the device of modified Hu. One would have been motivated in the wiring substrate of modified Hu and have the core material includes a glass fiber, in order to design a PCB with a reinforced base substrate, as indicated by Nakatani in ¶[0065], in the wiring board of modified Hu.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00.
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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