2DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The restriction requirement of June 5, 2026 is partially withdrawn. Specifically, the restriction requirement among Species 1-4 (see para. 2 of the restriction requirement) is withdrawn because there was no explanation on how these species are independent or distinct. Thus, claim 9 will be examined on the merits.
Applicant’s election without traverse of Species 1A and Species 2A (which together read on claims 1-20) in the reply filed on August 5, 2026, is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 20 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 20, which depends directly from claim 19, recites the limitation “each optical input/output device” in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination with regard to the prior art, “each optical input/output device” will be treated as --the optical input/output device--.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4, 7-8, 12-13, 14, 16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Pothukuchi et al. (US 20220085001), cited by Applicant in the Information Disclosure Statement filed on 4/26/2024, in view of Liu et al. (US 20210166991), the corresponding U.S. Patent cited by Applicant in the Information Disclosure Statement filed on 4/26/2024.
Regarding claim 1, Pothukuchi teaches, in Fig. 4A, a semiconductor package (400, [0039]) comprising:
a package substrate (405, [0039]) including a first (top) surface and a second (bottom) surface opposite the first surface;
a die (410, [0040]) disposed on the first (top) surface of the package substrate (405);
a stack structure (420/423/424/425, [0041]) disposed on the first (top) surface of the package substrate (405) and spaced apart from the die (410) in a horizontal direction (see Fig. 4A); and
a socket (421, [0041]) disposed between the first (top) surface of the package substrate (405) and the stack structure (420/423/424/425) and coupling the package substrate (405) and the stack structure (420/423/424/425) to each other,
wherein the stack structure (420/423/424/425) includes a photonic engine (420, [0041], a photonic engine usually has at least one optical integrated circuit chip).
Pothukuchi does not teach that the stack structure includes a plurality of optical integrated circuit chips stacked vertically with each other.
In a similar field of endeavor, Liu teaches, in Fig. 6, that the stack structure (photonic dies and electronic dies) includes a plurality of optical integrated circuit chips (photonic dies m and m+1, [0039]) stacked vertically with each other, in order to make chip-scale integration of an electronic integrated circuits (EIC) and photonic integrated circuits (PIC) "more cost effective, reliable, and highly integrated" ([0008]-[0009]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the stack structure of Pothukuchi with the vertically stacked optical integrated circuit chips of Liu, in order to make chip-scale integration of an electronic integrated circuits (EIC) and photonic integrated circuits (PIC) more cost effective, reliable, and highly integrated ([0008]-[0009]).
Regarding claim 2, Pothukuchi in view of Liu teaches the limitations of claim 1. Liu further teaches that the socket ([0046]) comprises either a land grid array (LGA) type socket or a pin grid array (PGA) type socket ([0043], [0049], LGA type).
Regarding claim 4, Pothukuchi in view of Liu teaches the limitations of claim 1. Liu further teaches, in Fig. 6, that the stack structure (photonic dies and electronic dies) further comprises an electronic integrated circuit chip (electronic die n, [0039]) disposed on an uppermost optical integrated circuit chip (photonic die n) among the plurality of optical integrated circuit chips.
Regarding claim 7, Pothukuchi in view of Liu teaches the limitations of claim 1. Pothukuchi in view of Liu further teaches an optical input/output connector (Pothukuchi Fig. 4A, 422, [0041]) spaced apart from the die (410) with the plurality of optical integrated circuit chips (420) therebetween (see Pothukuchi Fig. 4A).
Liu further teaches, in Fig. 12, that the optical input/output device (fiber, [0046]) includes an alignment pin (vertical part),
that the stack structure further comprises an intermediate substrate (glass) which is disposed between the socket ([0046]) and a lowermost optical integrated circuit chip (photonic die m+1) among the plurality of optical integrated circuit chips and includes an alignment hole (filled by “fiber”), and
the alignment pin (vertical part) of the optical input/output connector (fiber) is coupled to the alignment hole of the intermediate substrate (glass) (see Fig. 12).
Regarding claim 8, Pothukuchi in view of Liu teaches the limitations of claim 1. Pothukuchi further teaches, in Fig. 4A, a cover (426, [0011]) covering at least a portion of the stack structure (420/423/424/425) (see Fig. 4A);
Regarding claim 12, Pothukuchi in view of Liu teaches the limitations of claim 1. Liu further teaches, in Fig. 11, a plurality of connection terminals (1002, labelled in Fig. 10, [0046]) disposed between the first (top) surface of the package substrate (PCB, [0046]) and the socket ([0046]),
wherein the socket is connected to the package substrate (PCB) through the plurality of connection terminals (1002) (see Fig. 11), and
each connection terminal (1002) of the plurality of connection terminals comprises a solder ball or solder bump ([0046]).
Regarding claim 13, Pothukuchi in view of Liu teaches the limitations of claim 1. Pothukuchi further teaches, in Fig. 4A, that the socket (421) contacts the first (top) surface of the package substrate (405).
Regarding claim 14, Pothukuchi teaches, in Fig. 4A, a semiconductor package (400, [0039]) comprising:
a package substrate (405, [0039]) including a first (top) surface and a second (bottom) surface opposite the first surface;
a die (410, [0040]) disposed on the first (top) surface of the package substrate (405);
external connection terminals (bottom set of 421, [0041]) disposed on the second (bottom) surface of the package substrate (405);
a stack structure (420/423/424/425, [0041]) disposed on the first (top) surface of the package substrate (405) and spaced apart from the die (410) in a horizontal direction (see Fig. 4A), the stack structure including a photonic engine (420, [0041], a photonic engine usually has at least one optical integrated circuit chip);
a socket (421, [0041]) disposed between the stack structure (420/423/424/425) and the first (top) surface of the package substrate (405) and coupling the package substrate (405) to the stack structure (420/423/424/425); and
an optical input/output connector (422, [0041]) coupled to the photonic engine (420).
Pothukuchi does not teach that the stack structure includes a plurality of optical integrated circuit chips stacked vertically with each other, and that the optical input/output connector is coupled to each of the optical integrated circuit chips.
In a similar field of endeavor, Liu teaches, in Fig. 6, that the stack structure (photonic dies and electronic dies) includes a plurality of optical integrated circuit chips (photonic dies m and m+1, [0039]) stacked vertically with each other, and that the optical input/output connector (“fiber,” Fig. 11) is coupled to each of the optical integrated circuit chips (the external optical fiber connecting to photonic die m+1 would also be coupled to photonic die m),
in order to make chip-scale integration of an electronic integrated circuits (EIC) and photonic integrated circuits (PIC) "more cost effective, reliable, and highly integrated" ([0008]-[0009]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the stack structure of Pothukuchi with the vertically stacked optical integrated circuit chips of Liu, in order to make chip-scale integration of an electronic integrated circuits (EIC) and photonic integrated circuits (PIC) more cost effective, reliable, and highly integrated ([0008]-[0009]).
Regarding claim 16, Pothukuchi in view of Liu teaches the limitations of claim 14. Liu further teaches that the socket ([0046]) comprises either a land grid array (LGA) type socket or a pin grid array (PGA) type socket ([0043], [0049], LGA type).
Regarding claim 19, Pothukuchi teaches, in Fig. 4A, a semiconductor package (400, [0039]) comprising:
a package substrate (405, [0039]) including a first (top) surface and a second (bottom) surface opposite the first surface;
a die (410, [0040]) disposed on the first (top) surface of the package substrate (405) and connected to the package substrate (405) through a connection terminal (411, [0040]);
a stack structure (420/423/424/425, [0041]) disposed on the first (top) surface of the package substrate (405) and spaced apart from the die (410) in a horizontal direction (see Fig. 4A); and
a cover (426, [0011]) covering at least a portion of the stack structure (420/423/424/425) (see Fig. 4A);
an optical input/output connector (422, [0041]) spaced apart from the die (410) with the stack structure (420/423/424/425) therebetween (see Fig. 4A); and
a socket (421, [0041]) disposed between the first (top) surface of the package substrate (405) and the stack structure (420/423/424/425) and coupling the package substrate (405) and the stack structure (420/423/424/425) to each other,
wherein the stack structure (420/423/424/425) comprises:
a photonic engine (420, [0041], a photonic engine usually has at least one optical integrated circuit chip).
Pothukuchi does not teach that the stack structure comprises: a plurality of optical integrated circuit chips stacked vertically with each other; and an electronic integrated circuit chip on an uppermost optical integrated circuit chip among the plurality of optical integrated circuit chips, wherein the uppermost optical integrated circuit chip among the plurality of optical integrated circuit chips and the electronic integrated circuit chip are electrically connected to each other.
In a similar field of endeavor, Liu teaches, in Fig. 6, that the stack structure (photonic dies and electronic dies) comprises:
a plurality of optical integrated circuit chips (photonic dies m and m+1, [0039]) stacked vertically with each other; and
an electronic integrated circuit chip (electronic die n, [0039]) on an uppermost optical integrated circuit chip (photonic die n) among the plurality of optical integrated circuit chips,
wherein the uppermost optical integrated circuit chip (photonic die n) among the plurality of optical integrated circuit chips and the electronic integrated circuit chip (electronic die n) are electrically connected to each other (see Fig. 6, [0039]), in order to make chip-scale integration of an electronic integrated circuits (EIC) and photonic integrated circuits (PIC) "more cost effective, reliable, and highly integrated" ([0008]-[0009]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the stack structure of Pothukuchi with the vertically stacked optical integrated circuit chips and electronic integrated circuit chip of Liu, in order to make chip-scale integration of an electronic integrated circuits (EIC) and photonic integrated circuits (PIC) more cost effective, reliable, and highly integrated ([0008]-[0009]).
Claims 3, 5-6, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Pothukuchi et al. (US 20220085001), cited by Applicant in the Information Disclosure Statement filed on 4/26/2024, in view of Liu et al. (US 20210166991), the corresponding U.S. Patent cited by Applicant in the Information Disclosure Statement filed on 4/26/2024, and further in view of Duong et al. (US 20260118576).
Regarding claim 3, Pothukuchi in view of Liu teaches the limitations of claim 1. Liu further teaches, in Fig. 6, that the plurality of optical integrated circuit chips stacked vertically with each other (photonic dies m and m+1) include two optical integrated circuit chips vertically adjacent to each other (see Fig. 6).
Pothukuchi in view of Liu does not teach that the two optical integrated circuit chips are hybrid-bonded with each other.
In a similar field of endeavor, Duong teaches, in Fig. 2, that the two optical integrated circuit chips (104 and 106, [0023]) are hybrid-bonded with each other ([0046]), in order to increase the yield or reduce the required footprint of the optical integrated circuit chips ([0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical integrated circuit chips of Pothukuchi in view of Liu with the hybrid bonding of Duong, in order to increase the yield or reduce the required footprint of the optical integrated circuit chips ([0025]).
Regarding claim 5, Pothukuchi in view of Liu teaches the limitations of claim 4. Liu further teaches, in Fig. 6, that the uppermost optical integrated circuit chip (photonic die m) comprises through vias (TWI, [0029], [0039]), and
the electronic integrated circuit chip (electronic die n) and the uppermost optical integrated circuit chip (photonic die m) among the plurality of optical integrated circuit chips are electrically connected to each other through the through vias (TWI) (see Fig. 6, [0039]).
Pothukuchi in view of Liu does not teach that each of the optical integrated circuit chips comprises through vias.
In a similar field of endeavor, Duong teaches, in Fig. 2, that each of the optical integrated circuit chips (104 and 106, [0023]) comprises through vias (210 and 212, [0026]), in order to provide electrical connections between the PIC dies 104, 106 and/or the EIC die 102 ([0026]) and in order to increase the yield or reduce the required footprint of the optical integrated circuit chips ([0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical integrated circuit chips of Pothukuchi in view of Liu with the through vias of Duong, in order to provide electrical connections between the PIC dies 104, 106 and/or the EIC die 102 ([0026]) and to increase the yield or reduce the required footprint of the optical integrated circuit chips ([0025]).
Regarding claim 6, Pothukuchi in view of Liu teaches the limitations of claim 1. Pothukuchi further teaches, in Fig. 4A, an optical input/output device (422, [0041]) coupled to the stack structure (420/423/424/425) and spaced apart from the die (410).
Liu further teaches, in Fig. 6, that each of the optical integrated circuit chips (photonic dies m and m+1) comprises a groove recessed downward from an upper surface of each optical integrated circuit chip ([0029], [0039]; photonic die m has a groove from TWI, and photonic die m+1 has a groove from a photonic interconnect), and
in Fig. 12, the bottommost integrated circuit chip (photonic die m+1) and a respective optical input/output device ([0050], Fig. 12, connected to external optical fiber) are connected to each other through the groove (see Fig. 12 how photonic die m+1 is connected to the external optical fiber through the groove filled by a TWI).
Pothukuchi in view of Liu does not teach that each optical integrated circuit chip and a respective optical input/output device are connected to each other through the groove.
In a similar field of endeavor, Duong teaches, in Fig. 2, that each optical integrated circuit chip (104 and 106, [0023]) and a respective optical input/output device are connected to each other through the groove (filled by 210 and 212, [0026], each of 104 and 106 are connected to input/output connections 210/212), in order to provide electrical connections between the PIC dies 104, 106 and/or the EIC die 102 ([0026]) and in order to increase the yield or reduce the required footprint of the optical integrated circuit chips ([0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the connections of Pothukuchi in view of Liu with the connections of Duong, in order to provide electrical connections between the PIC dies 104, 106 and/or the EIC die 102 ([0026]) and to increase the yield or reduce the required footprint of the optical integrated circuit chips ([0025]).
Regarding claim 15, Pothukuchi in view of Liu teaches the limitations of claim 14. Pothukuchi in view of Liu does not teach that the external connection terminals comprise solder balls.
In a similar field of endeavor, Duong teaches, in Fig. 11, that the external connection terminals comprise solder balls (1128, [0086], [0076]), in order to make a package-on-package structure ([0086]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the external connection terminals of Pothukuchi in view of Liu with the the external connection terminals of Duong, in order to make a package-on-package structure ([0086]).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Pothukuchi et al. (US 20220085001), cited by Applicant in the Information Disclosure Statement filed on 4/26/2024, in view of Liu et al. (US 20210166991), the corresponding U.S. Patent cited by Applicant in the Information Disclosure Statement filed on 4/26/2024, and further in view of Chen et al. (US 20240096732).
Regarding claim 9, Pothukuchi in view of Liu teaches the limitations of claim 8. Pothukuchi in view of Liu does not teach that the cover includes a cover opening penetrating through a surface of the cover, and at least a portion of an upper surface of the stack structure is exposed to the outside of the semiconductor package through the cover opening.
In a similar field of endeavor, Chen teaches, in Fig. 2A, that the cover (214, [0034]) includes a cover opening (222a, [0037]) penetrating through a surface of the cover (214), and
at least a portion of an upper surface of the stack structure (206, [0033]) is exposed to the outside of the semiconductor package through the cover opening (222a),
in order to provide access to the stack ([0058]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the cover of Pothukuchi in view of Liu with the cover opening of Chen, in order to provide access to the stack ([0058]).
Regarding claim 10, Pothukuchi in view of Liu teaches the limitations of claim 8. Pothukuchi in view of Liu does not teach that the cover contacts the first surface of the package substrate.
In a similar field of endeavor, Chen teaches, in Fig. 2A, that the cover (214, 220a, 220c, [0034], [0036]) contacts the first (top) surface of the package substrate (204, [0032]), in order to increase the rigidity of the cover ([0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the cover of Pothukuchi in view of Liu with the cover structure of Chen, in order to increase the rigidity of the cover ([0041]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Pothukuchi et al. (US 20220085001), cited by Applicant in the Information Disclosure Statement filed on 4/26/2024, in view of Liu et al. (US 20210166991), the corresponding U.S. Patent cited by Applicant in the Information Disclosure Statement filed on 4/26/2024, and Chen et al. (US 20240096732), and further in view of Tahkur et al. (US 20220114121), cited by Applicant in the Information Disclosure Statement filed on 4/26/2024.
Regarding claim 11, Pothukuchi in view of Liu and Chen teaches the limitations of claim 10. Pothukuchi further teaches, in Fig. 4A, that the semiconductor package further comprises an optical input/output connector (422, [0041]) spaced apart from the die (410) with the stack structure (420/423/424/425) therebetween.
Pothukuchi in view of Liu and Chen does not teach that the cover includes a cover hole in one side surface of the cover, and the optical input/output connector is connected to the optical integrated circuit chips through the cover hole.
In a similar field of endeavor, Tahkur teaches, in Fig. 1A, that the cover (114, [0017]) includes a cover hole (filled by 112) in one side (right) surface of the cover (114), and
the optical input/output connector (112, [0019]) is connected to the optical integrated circuit chips (106) through the cover hole (see Fig. 1A),
in order to protect the photonic die while still allowing it receive optical I/O signals.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the cover of Pothukuchi in view of Liu and Chen with the cover hole of Tahkur, in order to protect the optical integrated circuit chips while still allowing them to receive optical I/O signals.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Pothukuchi et al. (US 20220085001), cited by Applicant in the Information Disclosure Statement filed on 4/26/2024, in view of Liu et al. (US 20210166991), the corresponding U.S. Patent cited by Applicant in the Information Disclosure Statement filed on 4/26/2024, and further in view of Li et al. (WO 2024066603 A1, citations made hereinafter to the attached English Machine translation).
Regarding claim 17, Pothukuchi in view of Liu teaches the limitations of claim 16. Liu further teaches that the socket ([0046]) comprises either a land grid array (LGA) type socket ([0043], [0049]).
Pothukuchi further teaches that the semiconductor package further comprises a cover (426, [0011]) covering at least a portion of the stack structure (420/423/424/425) (see Fig. 4A).
Pothukuchi in view of Liu does not teach that the cover is coupled to the socket through a bolt.
In a similar field of endeavor, Li teaches that the cover (201, pg. 15, 7th para. starting with “FIG9”) is coupled to the socket (pg. 18, 5th para. starting with “S160”, layer between 130 and 202) through a bolt (pg. 15, first two lines), in order to better fix the cover to the package substrate (pg. 15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the cover of Pothukuchi in view of Liu with the cover bolting of Li, in order to better fix the cover to the package substrate (pg. 15).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Pothukuchi et al. (US 20220085001), cited by Applicant in the Information Disclosure Statement filed on 4/26/2024, in view of Liu et al. (US 20210166991), the corresponding U.S. Patent cited by Applicant in the Information Disclosure Statement filed on 4/26/2024, and further in view of Yu et al. (US 20230012157), cited by Applicant in the Information Disclosure Statement filed on 4/26/2024.
Regarding claim 18, Pothukuchi in view of Liu teaches the limitations of claim 14. Liu further teaches, in Fig. 6, that each of the optical integrated circuit chips (photonic dies m and m+1 comprises: a body.
Pothukuchi in view of Liu does not teach that each of the optical integrated circuit chips comprises: a through via penetrating the body; and bonding pads disposed on an upper surface and a lower surface of the body, wherein the through via is connected to one of the bonding pads.
In a similar field of endeavor, Yu teaches, in Fig. 18, that each of the optical integrated circuit chips (64 and 164, [0042]) comprises:
a through via (60 and 160, [0050]) penetrating the body; and
bonding pads (62 and 162 for 164, and 40 and 62 for 64, [0032], [0041], [0048]) disposed on an upper surface and a lower surface of the body,
wherein the through via is connected to one of the bonding pads (60 is connected to either 62, and 160 is connected to 162),
in order to reduce the footage of the photonic package and “provide optical communication between the photonic dies without the need of using optical fibers” ([0070]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical integrated circuit chips of Pothukuchi in view of Liu with the through vias and bonding pads of yu in order to reduce the footage of the photonic package and provide optical communication between the optical integrated circuit chips without the need of using optical fibers ([0070]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Pothukuchi et al. (US 20220085001), cited by Applicant in the Information Disclosure Statement filed on 4/26/2024, in view of Liu et al. (US 20210166991), the corresponding U.S. Patent cited by Applicant in the Information Disclosure Statement filed on 4/26/2024, and further in view of Krichevsky et al. (US 20220404546).
Regarding claim 20, Pothukuchi in view of Liu teaches the limitations of claim 19. Liu further teaches, in Fig. 6, that each of the optical integrated circuit chips (photonic dies m and m+1) comprises a groove recessed downward from an upper surface thereof ([0029], [0039]; photonic die m has a groove from TWI, and photonic die m+1 has a groove from a photonic interconnect).
Pothukuchi further teaches, in Figs. 3 and 4A, that each optical input/output device (422, labelled as 322 in Fig. 3) includes an optical fiber coupled to each of the optical integrated circuit chips (420, labelled as 320 in Fig. 3) ([0026]).
Pothukuchi in view of Liu does not teach that the optical fiber is disposed in the groove.
In a similar field of endeavor, Krichevsky teaches, in Fig. 3A, that the optical fiber (113, [0040]) is disposed in the groove ([0068]-[0069], 305 of first PIC die 301 and 313 of second PIC die 302), in order to “mechanically constrain the optical wire” ([0064]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the optical fiber configuration of Pothukuchi in view of Liu with the optical fiber configuration of Krichevsky, in order to mechanically constrain the optical wire ([0064]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kang et al. (US 20250125312) teaches the limitations of claim 1, but is not prior art (effective filing date 10/11/2023).
Kang et al. (US 202501253210) teaches the limitations of claim 1, but is not prior art (effective filing date 10/11/2023).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is 703-756-4644. The examiner can normally be reached Monday - Friday 12:30-9 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached on 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights