DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/26/2024 was filed before the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 12,002,875. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 of U.S. Patent No. 12,002,875 recites all of the limitations in claim 1 of the instant application.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 12,002,875. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 of U.S. Patent No. 12,002,875 recites all of the limitations in claim 2 of the instant application.
Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 9 of U.S. Patent No. 12,002,875. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 9 of U.S. Patent No. 12,002,875 recites all of the limitations in claim 3 of the instant application. Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 12,002,875. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 of U.S. Patent No. 12,002,875 recites all of the limitations in claim 6 of the instant application. Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 12,002,875. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 of U.S. Patent No. 12,002,875 recites all of the limitations in claim 8 of the instant application. Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 12,002,875. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 of U.S. Patent No. 12,002,875 recites all of the limitations in claim 9 of the instant application.
Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 12,002,875. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 of U.S. Patent No. 12,002,875 recites all of the limitations in claim 15 of the instant application.
Prior art of record
Re claim 1, Kim et al. (2016/0027918) teaches a semiconductor device (Fig. 11G) comprises: a substrate (310) having a first fin (ACT, “left fin”) and a second fin (ACT, “right fin”); an isolation region (330) over the substrate (310) between the first fin (ACT, “left fin”) and the second fin (ACT, “right fin”); a source/drain region (380) over the first fin (ACT, “left fin”), the source/drain region (380) comprising a plurality of silicon germanium layers (384, 386, 388), yet remains explicitly silent to wherein an uppermost silicon germanium layer of the plurality of silicon germanium layers has the highest germanium concentration of the source/drain region; and a source/drain contact, wherein at least a portion of the source/drain contact is in contact with the uppermost silicon germanium layer. Re claim 8, Kim et al. (2016/0027918) teaches a semiconductor device (Fig. 11G) comprises: a substrate (310) having a first fin (ACT, “left fin”) and a second fin (ACT, “right fin”); an isolation region (330) over the substrate (310) between the first fin (ACT, “left fin”) and the second fin (ACT, “right fin”); a plurality of semiconductor regions (380) over the first fin (ACT, “left fin”) and the second fin (ACT, “right fin”), wherein each of the plurality of semiconductor regions (380) comprise silicon germanium [105], yet remains explicitly silent to wherein an uppermost semiconductor region of the plurality of semiconductor regions has the highest germanium concentration of the plurality of semiconductor regions, wherein the uppermost semiconductor region extends over the first fin and the second fin; and a source/drain contact, wherein the source/drain contact contacts the uppermost semiconductor region. Re claim 15, Kim et al. (2016/0027918) teaches a method of forming a semiconductor device (Figs. 11A-G), the method comprising: forming an isolation region (330) adjacent a first fin (ACT, “left fin”) and a second fin (ACT, “right fin”), the first fin (ACT, “left fin”) and the second fin (ACT, “right fin”) protruding above an upper surface of the isolation region (330); forming a first gate structure (420) over the first fin (ACT, “left fin”) and the second fin (ACT, “right fin”); forming a source/drain region (380) over the first fin (ACT, “left fin”) and the second fin (ACT, “right fin”), forming the source/drain region (380) comprising forming a plurality of silicon germanium layers (384, 386, 388), yet remains explicitly silent to wherein an uppermost silicon germanium layer of the plurality of silicon germanium layers has the highest germanium concentration of the source/drain region, wherein a first lower silicon germanium layer over the first fin is spaced apart from a second lower silicon germanium over the second fin; and forming a source/drain contact, wherein at least a portion of the source/drain contact is in contact with the uppermost silicon germanium layer.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record does not anticipate or make obvious the device of claim 1, including each of the limitations and specifically wherein an uppermost silicon germanium layer of the plurality of silicon germanium layers has the highest germanium concentration of the source/drain region; and a source/drain contact, wherein at least a portion of the source/drain contact is in contact with the uppermost silicon germanium layer, for the same reasons as mentioned for claim 1 in the prior art of record above. The prior art of record does not anticipate or make obvious the device of claim 8, including each of the limitations and specifically wherein an uppermost semiconductor region of the plurality of semiconductor regions has the highest germanium concentration of the plurality of semiconductor regions, wherein the uppermost semiconductor region extends over the first fin and the second fin; and a source/drain contact, wherein the source/drain contact contacts the uppermost semiconductor region, for the same reasons as mentioned for claim 8 in the prior art of record above. The prior art of record does not anticipate or make obvious the method of claim 15, including each of the limitations and specifically wherein an uppermost silicon germanium layer of the plurality of silicon germanium layers has the highest germanium concentration of the source/drain region, wherein a first lower silicon germanium layer over the first fin is spaced apart from a second lower silicon germanium over the second fin; and forming a source/drain contact, wherein at least a portion of the source/drain contact is in contact with the uppermost silicon germanium layer, for the same reasons as mentioned for claim 15 in the prior art of record above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
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