Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of invention I, in the reply filed on June 30, 2026, is acknowledged. The traversal is on the grounds that there is no serious burden to search both inventions. This is not found persuasive because the applicant has . In addition, prior art that reads on one invention may not necessarily read on the other (e.g., art that discloses the claimed apparatus may not necessarily disclose the claimed process of manufacture of said apparatus), thus creating a search burden.
The requirement is still deemed proper and is therefore made FINAL.
Claims 9-13 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on June 30, 2026.
Specification
The abstract of the disclosure is objected to because in lines 4 and 5, “plurality substrate units” should be “plurality of substrate units”. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
In paragraph [0005], both instances of “plurality substrate units” should be “plurality of substrate units”.
In paragraph [0026], “plurality substrate units” should be “plurality of substrate units”.
In paragraph [0043], “providing interconnect” should be “providing an interconnect”.
In paragraph [0048], “providing interconnect” should be “providing an interconnect”.
Appropriate correction is required.
Claim Objections
Claims 1, 3-4, and are objected to because of the following informalities:
In claim 1, lines 5 and 7, both instances of “plurality substrate units” should be “plurality of substrate units”.
In claim 3, line 3, “plurality substrate units” should be “plurality of substrate units”.
In claim 4, line 2, “providing interconnect” should be “providing an interconnect”.
In claim 8, line 1, “plurality substrate units” should be “plurality of substrate units”.
Appropriate correction is required.
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701
818
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Figs. 5A and 5B of Liao, reproduced with annotations added by the examiner.
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626
712
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Figs. 5C and 5D of Liao, reproduced with annotations and lines marking the singulation areas and the first and second portions of the trench added by the examiner.
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319
791
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Fig. 5E of Liao, reproduced with annotation added by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 5-8 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Liao et. al., Pub. No. US 2011/0260301, hereafter referred to as Liao.
Regarding claim 1, Liao teaches all of the limitations of the claim in Figs. 5A-5E, reproduced above with annotations added by the examiner: “A method for making a semiconductor device, comprising: providing a package” (Figs. 5A-5E) “comprising: a substrate” ([0048]; Fig. 5A, substrate 500) “having a front substrate surface” (Fig. 5A, upper surface of the substrate 500) “and a back substrate surface opposite to the front substrate surface” (Fig. 5A, lower surface of the substrate 500), “wherein the substrate comprises a plurality of singulation areas separating the substrate into a plurality substrate units” ([0048]; Figs. 5A and 5B, substrate units 102 and 102’ and Fig. 5C, singulation areas; also see [0053]: “To facilitate proper positioning of the substrate 500 during subsequent singulation operations, fiducial marks can be formed in the molded structure 526, such as using laser marking. Alternatively, or in conjunction, fiducial marks can be formed adjacent to a periphery of the substrate 500.”); “a plurality of first electronic components mounted on the front substrate 3surface and within the plurality substrate units, respectively” ([0052]; Figs. 5A and 5B, semiconductor devices 108a-c; note that the semiconductor devices 108a-c are all mounted on the front surface of the substrate 500 and on the substrate units 102 and 102’); “and an encapsulant formed on the front substrate surface and encapsulating the plurality of first electronic components” ([0053]; Fig. 5C, molded structure 514); “forming a plurality of trenches at the plurality of singulation areas, respectively” ([0054]; Fig. 5D, cutting slits 520a and 520b), “wherein each of the plurality of trenches has a first portion extending through the encapsulant” (Fig. 5D, first portion of the trench) “and a second portion extending through the encapsulant and the substrate” (Fig. 5D, second portion of the trench); “and forming an electromagnetic interference (EMI) shield to cover the encapsulant and lateral surfaces of the plurality of substrate units exposed by the second portions of the plurality of trenches” ([0056]; Fig. 5E, EMI coating 522; note that the EMI coating covers the exposed surfaces of the molded structure 514 and the substrate 500).
Regarding claim 2, Liao further teaches “The method of claim 1, wherein forming the plurality of trenches at the plurality of singulation areas comprises: removing a portion of the encapsulant at the plurality of singulation areas to form the first portion of the trench and an upper portion of the second portion of the trench” ([0054]: “Referring to FIG. 5C and FIG. 5D, the “front-side” singulation is carried out using a saw 518, which forms cutting slits, including cutting slits 520a and 520b. In particular, the cutting slits 520a and 520b extend downwardly and completely through the molded structure 526…”); “and removing a first portion of the substrate under the upper portion of the second portion of the trench to form a lower portion of the second portion of the trench” ([0054]: “In particular, the cutting slits 520a and 520b extend downwardly and completely through… the substrate 500…”).
Regarding claim 5, Liao further teaches “The method of claim 1, further comprising: singulating the substrate into a plurality of semiconductor devices by removing a second portion of the substrate under the first portions of the plurality of trenches” ([0054]: “In particular, the cutting slits 520a and 520b extend downwardly and completely through… the substrate 500…”).
Regarding claim 6, Liao further teaches “The method of claim 1, wherein each of the plurality of singulation areas forms a closed track enclosing a respective substrate unit” ([0048]: “The substrate 500 can be implemented in… an array manner, in which the multiple substrate units are arranged in a two-dimensional fashion.”; Fig. 5B; note that, in an array arrangement, the singulation areas for the individual units must form a closed track).
Regarding claim 7, Liao further teaches “The method of claim 1, wherein the plurality of substrate units are arranged in a row or in an array” ([0048]; Fig. 5B).
Regarding claim 8, Liao further teaches “The method of claim 1, wherein each of the plurality substrate units comprises a grounding element” ([0049]; Fig. 5A, grounding vias 502a-d) “exposed by the second portion of a respective trench” ([0055]: “Still referring to FIG. 5D, the saw 518 is laterally positioned and substantially aligned with each grounding via, such that a resulting cutting slit removes a certain volume or weight percentage of the grounding via…”; Fig. 5D; note that portions of the grounding vias 118a and 118b are exposed within the second portion of the trench), “and the EMI shield is electrically connected to the grounding element” (Fig. 5E; note that the EMI coating 522 is in contact with the grounding vias 118a and 118b).
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Figs. 6a and 6b of Yang, reproduced with annotations added by the examiner.
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636
769
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Figs. 6c and 6d of Yang, reproduced with annotations added by the examiner.
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298
765
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Fig. 6e of Yang, reproduced with annotation added by the examiner.
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314
452
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Fig. 7a of Yang, reproduced with annotations added by the examiner.
Claims 1 and 3-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et. al., Pub. No. US 2020/0161252, hereafter referred to as Yang.
Regarding claim 1, Yang teaches all of the limitations of the claim in Figs. 1a and 6a-6f, reproduced above with annotations added by the examiner: “A method for making a semiconductor device, comprising: providing a package” (Figs. 6a-6f) “comprising: a substrate” ([0039]; Fig. 6a, interposer substrate 140) “having a front substrate surface” (Fig. 6b, lower surface of the interposer substrate 140) “and a back substrate surface opposite to the front substrate surface” (Fig. 6b, upper surface of the interposer substrate 140), “wherein the substrate comprises a plurality of singulation areas separating the substrate into a plurality substrate units” ([0040]; Figs. 6a and 6b, saw streets 152 and molded laser semiconductor packages (MLP units) 262); “a plurality of first electronic components mounted on the front substrate surface and within the plurality substrate units, respectively” ([0039]; Fig. 6a, inductor 202, capacitor 204, and semiconductor package 206, hereafter referred to as first components; note that the first components are mounted on the front surface of the interposer substrate 140 and on each of the MLP units 262); “and an encapsulant formed on the front substrate surface and encapsulating the plurality of first electronic components” ([0039]; Fig. 6a, encapsulant 252); “forming a plurality of trenches at the plurality of singulation areas, respectively” ([0040]; Fig. 6c, trenches 260), “wherein each of the plurality of trenches has a first portion extending through the encapsulant” (Fig. 6c, first portion of the trench) “and a second portion extending through the encapsulant and the substrate” (Fig. 6c, second portion of the trench); “and forming an electromagnetic interference (EMI) shield to cover the encapsulant and lateral surfaces of the plurality of substrate units exposed by the second portions of the plurality of trenches” ([0041]; Fig. 6d, shielding layer 266; note that the shielding layer 266 covers the exposed surfaces of the encapsulant 252 and the interposer substrate 140).
Regarding claim 3, Yang further teaches “The method of claim 1, further comprising: mounting a plurality of second electronic components on the back substrate surface and within the plurality substrate units, respectively” ([0039]; Fig. 6b, semiconductor die 104; note that the semiconductor die 104 is mounted on the second surface of the interposer substrate 140 and on each of the MLP units 262).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yang.
Regarding claim 4, the embodiment of Yang shown in Figs. 6a-6e teaches “The method of claim 3”, but does not explicitly teach “wherein the plurality of second electronic components comprise a clip or a connector for providing interconnect between the semiconductor device and an external device.” Yang does, however, teach conductive pillars and bumps extending outside of the EMI shield ([0042]; Fig. 6e, conductive pillars 160 and bumps 182; also see [0043]: “FIGS. 7a and 7b illustrate incorporating the above described MLP units… into an electronic device… Bumps 182 are reflowed onto conductive layer 302 of PCB 300 to physically attach and electrically connect MLP unit 188 to the PCB.” and Fig. 7a and note that the MLP unit 188 in Fig. 7a may be replaced with one of the MLP units 262 in Figs. 6a-6e).
The embodiment of Yang shown in Fig. 7a, however, show a different MLP unit ([0043]; Fig. 7a, MLP unit 188) bonded to a PCB ([0043]; Fig. 7a, PCB 300) through similar pillars and bumps ([0043]: “FIGS. 7a and 7b illustrate incorporating the above described MLP units… into an electronic device… Bumps 182 are reflowed onto conductive layer 302 of PCB 300 to physically attach and electrically connect MLP unit 188 to the PCB.”; Fig. 7a, conductive pillars 160 and bumps 182).
The MLP unit 188 of the embodiment of Fig. 7a may be replaced with one of the MLP units 262 shown in the embodiment of Figs. 6a-6e, which is bonded to the PCP through the conductive pillars and bumps. The combined device teaches “wherein the plurality of second electronic components comprise a clip or a connector for providing interconnect between the semiconductor device and an external device” ([0042]; Fig. 6e, conductive pillars 160 and bumps 182; also see [0043]: “FIGS. 7a and 7b illustrate incorporating the above described MLP units… into an electronic device… Bumps 182 are reflowed onto conductive layer 302 of PCB 300 to physically attach and electrically connect MLP unit 188 to the PCB.” and Fig. 7a; note that the MLP unit 188 in Fig. 7a is replaced with one of the MLP units 262 in Figs. 6a-6e in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have mounted one of the MLP units 262 of the embodiment of Yang shown in Figs. 6a-6e on a PCB in the same way as the MLP unit 188 shown in the embodiment of Yang shown in Fig. 7a because Yang suggests that any of the MLP units described therein can be so mounted ([0043]: “FIGS. 7a and 7b illustrate incorporating the above described MLP units, e.g., MLP unit 188, into an electronic device.”), mounting them on a PCB would be required for them to perform their intended function, and it would be a simple substitution of one element for another.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert E Throckmorton whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Monday to Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.E.T./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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