DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/27/2024, 02/04/2025, and 07/31/2025 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restriction
Applicant’s election without traverse of a product claim, claims 1-15, 19, 20 in the reply filed on 6/15/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 15, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dasgupta (US 20140094223 A1) in view of Ono (US 20020050595 A1)
Regarding claim 1, Dasgupta discloses (Fig. 2A) An integrated circuit (Fig. 2A), comprising:
a substrate (100, Fig. 1B); a first nucleation layer (104,105), located on the substrate; a buffer layer (106), located on the first nucleation layer; a channel layer (107), located on the buffer layer; a barrier layer (109), located on the channel layer; and a source (235), a drain (245), and a gate (220), each separately located on the barrier layer,
Dasgupta is silent regarding a dislocation density of the buffer layer is less than 1e8/cm2.
Ono discloses a HEMT device having a buffer layer with a dislocation density of less than 2000/cm2 (¶ [0008]) to reduce crystal defects and improve performance (¶ [0039]). As such, it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to substitute the buffer layer of Dasgupta for the buffer layer of Ono to alleviate the lattice mismatch and improve product performance.
Regarding claim 2, Dasgupta in view of Ono discloses the device of claim 1. Ono further discloses the dislocation density of the buffer layer is less than 1e6/cm² (¶ [0008]).
Regarding claim 15, Dasgupta in view of Ono discloses the device of claim 1. Dasgupta further discloses the integrated circuit is a high electron mobility transistor (HEMT, (¶ [0016]).
Regarding claim 19, Dasgupta discloses (Fig. 2A) An electronic device (Fig. 2A), comprising-: a circuit board (package IC mounted onto a circuit board, ¶ [0002]) ; and the integrated circuit (Fig. 2A), wherein the integrated circuit comprises: a substrate (100, Fig. 1A); a first nucleation layer (104,105), located on the substrate; a buffer layer (106), located on the first nucleation layer; a channel layer (107), located on the buffer layer; a barrier layer (109), located on the channel layer; and a source (235), a drain (245), and a gate (220), each separately located on the barrier layer.
Dasgupta is silent regarding a dislocation density of the buffer layer is less than 1e8/cm2.
Ono discloses a HEMT device having a buffer layer with a dislocation density of less than 2000/cm2 (¶ [0008]) to reduce crystal defects and improve performance (¶ [0039]). As such, it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to substitute the buffer layer of Dasgupta for the buffer layer of Ono to alleviate the lattice mismatch and improve product performance.
Regarding claim 20, Dasgupta discloses (Fig. 2A) A power amplifier (power amplification, ¶ [0016]), comprising: a circuit board (package IC mounted onto a circuit board, ¶ [0002]) ;and the integrated circuit (Fig. 2A), wherein the integrated circuit comprises: a substrate (100, Fig. 1B);a first nucleation layer (104, 105), located on the substrate; a buffer layer (106), located on the first nucleation layer; a channel layer (107), located on the buffer layer; a barrier layer (109), located on the channel layer; and a source (235), a drain (245), and a gate (220), separately located on the barrier layer,
Dasgupta is silent regarding a dislocation density of the buffer layer is less than 1e8/cm2.
Ono discloses a HEMT device having a dislocation density of less than 2000/cm2 (¶ [0008]) to reduce crystal defects and improve performance (¶ [0039]). As such, it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to substitute the buffer layer of Dasgupta for the buffer layer of Ono to alleviate the lattice mismatch and improve product performance.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dasgupta (US 20140094223 A1) in view of Ono (US 20020050595 A1) and Lee (US 20140299885 A1)
Regarding claim 3, Dasgupta in view of Ono discloses the device of claim 1. Dasgupta is silent regarding the lattice mismatch between the first nucleation layer and the buffer layer is less than 2%. Lee discloses that lattice constants and thermal expansion coefficients affect semiconductor thin film defects ([0008]). Lee discloses examples for the lattice constant difference between sublayers of buffer layer is less than 1% and the lattice constant between buffer layer and nucleation layer more than 4%. As such, when the general conditions of a claim are disclosed in the prior art (lattice constant difference between layers), it is not inventive to discover the optimum or workable ranges (lattice constant difference between nucleation layer and buffer layer) by routine experimentation. MPEP 2144.05
Thus, one of ordinary skill in the art before the effective filing date of the invention would have selected the lattice constant difference of less than 2% between the nucleation layer and the buffer layer to reduce cracks between layers (Lee: ¶ [0008]).
Claim(s) 4-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dasgupta (US 20140094223 A1) in view of Ono (US 20020050595 A1) and Cheng (US 20230238446 A1)
Regarding claim 4, Dasgupta in view of Ono discloses the device of claim 1. Das Dasgupta further discloses both the first nucleation layer (104, 105) and buffer layer comprising of AlInN (¶¶ [0033, 0047]) but is silent regarding the buffer layer comprises doped GaN or doped AlGaN.
Cheng discloses (¶ [0055]) a HEMT device (Fig. 10) including a nucleation layer and a buffer layer, each layer comprising at least one of Group III nitride-based materials, GaN, AlN, InN, AlGaN, InGaN, AlInN, or AlInGaN. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to select from a finite number of materials from Group III nitride-based materials to yield predictable results, having buffer layer comprising GaN and nucleation layer comprising AlInN.
Regarding claim 5, Dasgupta in view of Ono and Cheng discloses the device of claim 4. Dasgupta discloses (¶ [0026]) the Indium mol of graded layer 105 ranges from 0 to 18% (y is greater than 0.82 and Indium mol is 1-y).
Regarding claim 6, Dasgupta in view of Ono and Cheng discloses the device of claim 5. Dasgupta discloses the atomic percentage of Sc or In in the first nucleation layer ranges from 15% to 20%. (¶ [0026] disclosing the Indium mol of graded layer 105 ranges from 0 to 18%; y is greater than 0.82 and Indium mol is 1-y).
Regarding claim 7, Dasgupta in view of Ono and Cheng discloses the device of claim 6. Dasgupta discloses the atomic percentage of Sc in the first nucleation layer is 18.75%, or the atomic percentage of In in the first nucleation layer is 17% (¶ [0026] disclosing the Indium mol of graded layer 105 ranges from 0 to 18%; y is greater than 0.82 and Indium mol is 1-y).
Regarding claim 8, Dasgupta in view of Ono and Cheng discloses the device of claim 4. Dasgupta discloses an atomic percentage of Sc or In in a surface that is of the first nucleation layer and on a side that is in contact with the substrate is less than an atomic percentage of Sc or In in a surface that is of the first nucleation layer and on a side that is in contact with the buffer layer (¶ [0026]) disclosing in one such AlyIn1-yN embodiment (for layer 105), y decreasing from approximately 1 nearest the nucleation layer toward approximately x nearest the lattice matched AlxIn1-xN layer 106. Thus, the Indium content of (104,105) is largest near the buffer layer).
Regarding claim 9, Dasgupta in view of Ono and Cheng discloses the device of claim 8, Dasgupta discloses an atomic percentage of Sc in the first nucleation layer changes ranges from 0% to 18%; or an atomic percentage of In in the first nucleation layer changes ranges from 0% to 17% (¶ [0026] disclosing the Indium mol of graded layer ranges from 0 to 18%; y is greater than 0.82 and Indium mol is 1-y).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dasgupta (US 20140094223 A1) in view of Ono (US 20020050595 A1) and Nakata (US 20120001194 A1) and Dreizin (US 20100032064 A1)
Regarding claim 10, Dasgupta in view of Ono discloses the integrated circuit according to claim 1. Dasgupta further discloses (Fig. 2A): a second nucleation layer (105) located between the first nucleation layer (104, 105) and the buffer layer (106) but is silent regarding a quantity of grain boundaries in the second nucleation layer is less than a quantity of grain boundaries in the first nucleation layer.
Nakata discloses (¶ [0009]) a grain size is inversely proportional to the density of grain boundary; ¶ [0029] a grain size decrease degrading the crystal quality of a layer; and ¶ [0037] a grain size increase resulting in reducing density of grain boundaries and reducing crystal defects.
Dreizin discloses (¶ [0109]) a denser oxide layer can slow down the oxidation rate through the grain boundary diffusion process.
Thus, it is predictable to place a denser layer of grain boundaries closer to the substrate to slow down diffusion to the substrate and a less dense layer above it for better crystal quality.
As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to place a higher dense layer closer to the substrate and a less dense layer to join with above layer for optimal performance.
Claim(s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dasgupta (US 20140094223 A1) in view of Ono (US 20020050595 A1) and Lim (WO 2011032949 A1)
Regarding claim 11, Dasgupta in view of Ono discloses the integrated circuit according to claim 1. Dasgupta further discloses a surface density of a two- dimensional electron gas formed by using the barrier layer (¶ [0029]) but is silent regarding the two-dimensional electron gas surface density is greater than 1e13 /cm².
Lim (WO 2011032949 A1) discloses (last para. Pg. 39) the 2DEG density being more than 2e13 /cm² achieved by using AlGaInN barrier layer over AlGaN and AlInN barrier layers; with the latter, achieving a 1.5e13/ cm² surface electron density is almost impossible. As such, it would have been obvious to one of ordinary skill in the art before the filling date of the invention to substitute the barrier layer of Lim using AlGaInN for the barrier layer of Dasgupta to induce a larger surface electron density for higher drain current.
Regarding claim 12, Dasgupta in view of Ono and Lim discloses the integrated circuit according to claim 11. Dasgupta discloses a two – dimensional electron gas formed between the channel layer and the barrier layer (Fig. 2A). Lim (WO 2011032949 A1) discloses (last para. Pg. 39) the 2DEG density being more than 2e13 /cm2 achieved by using AlGaInN barrier layer over AlGaN and AlInN barrier layers.
Regarding claim 13, Dasgupta in view of Ono and Lim discloses the integrated circuit according to claim 11. Dasgupta further discloses the channel layer comprises GaN (¶ [0019]), and the barrier layer comprises AlScN, AlInN, or AlN (¶ [0053]).
Regarding claim 14, Dasgupta in view of Ono and Lim discloses the integrated circuit according to claim 11. Dasgupta further discloses the substrate comprises Si or SiC (¶ [0047]).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Keller (US 20140264455 A1) and Hudait (US 20080210927 A1) disclose a HEMT device with a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a transistor with gate, source/drain.
Conclusion
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/DTH/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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