DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, claims 1-7 and 16-20 in the reply filed on 9/8/2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first overlay shift being greater than the second overlay shift from claim 27 must be shown or the feature(s) canceled from the claim(s). While figure 14D appears to be intended to show this feature, due to the difficult to read nature of the drawing, it is unclear exactly what that figure is trying to show regarding that feature. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
• In paragraph 0062, line 12, “maxiumu” should read “maximum”
• In paragraph 0065 line 2 “Not mean to be bound by theory” should read “Not meant to be bound by theory”
• In paragraph 0079 and 0083 line 2, “fromed” should read “formed”
Appropriate correction is required.
Claim Objections
The numbering of claims is not in accordance with 37 CFR 1.126 which requires the original numbering of the claims to be preserved throughout the prosecution. When claims are canceled, the remaining claims must not be renumbered. When new claims are presented, they must be numbered consecutively beginning with the number next following the highest numbered claims previously presented (whether entered or not).
Misnumbered claim has been renumbered to .
Claim 17 is objected to because of the following informalities: "etching through fin structure" should read "etching through the fin structure". Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19-20 and 22-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 19 and 20, these claims recite the limitation "the first depth" in lines 1 and 2, respectivel. There is insufficient antecedent basis for this limitation in the claim. The limitation “a first depth” first appears in that claim tree in claim 18, but these two claims do not depend on claim 18. It is unclear whether the first depth in claim 19 and 20 are intended to refer to that depth, or some other depth, rendering the claim indefinite. For examination, claim 19 and 20 wee treated as depending on claim 18 instead of 17.
Regarding claims 20, the claim recites that “the second width is greater than the first depth”. The claim previously introduces the first width and the second width, so it naturally would follow that they would be the dimensions being compared. Furthermore, as is best understood from the specification, it only makes sense to compare these widths together, rather than to compare the second width to the first depth, which have no correlation drawn together in the specification where it is never said that the second width would be greater than the first depth. For examination, this claim was treated as “the second width is greater than the first width.”
Regarding claim 24, The term “about” in claim 24, line 2 is a relative term which renders the claim indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Therefore, it is unclear exactly what the ratio between the maximum width and the necking width would need to be in order to fall within the scope of the claim.
Regarding claims 22-28, these claims contain several antecedent basis issues. “the maximum width” in claims 24, and 28, “the second level” in claim 25 and “the first level” in claims 26 and 27 all lack antecedent basis. Claim 22 reintroduces a passivation layer, making it unclear whether it’s referring to the previous passivation layer, or introducing a new one. Claim 23 inherits this rejection from dependency on claim 22. It appears that these claims were intended to depend directly or indirectly from claim 21, which would fix all of these issues, so for the purposes of examination, claims 22, 24, 25, 26, and 28 will be treated as depending off of claim 21.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
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Chen figures 10A-10C and (11-16)A
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 20190165137 A1), hereinafter referred to as "Chen".
Regarding claim 1, Chen discloses a method comprising: forming a fin structure (24 in figure 10A) on a substrate (20 in figure 10A) along a first direction (the fins extend into and out of the page), a gate structure across the fin structure (48 in figure 10A), and source/drain regions on opposite sides of the gate structure (36 in figure 10B); depositing a mask layer over the gate structure (52 in figure 10A); forming a pattern in the mask layer (Chen paragraph 0040), wherein the pattern comprises an elongated opening formed over a portion of the gate structure (see opening 54 in figure 10C); and etching the gate structure through the elongated opening to expose the fin structure (etch process in figure 11A exposes fins 24); etching the fin structure to a first depth (see figure 12A); depositing an enhanced passivation layer (liner 62 in figure 13A); performing a break-through etch process (etch in figure 14A breaks through line 62 covering the fins); and etching the fin structure and the substrate to a second depth to form an isolation opening (Chen figure 15A); and filling the isolation opening with a dielectric material (66 in figure 16A).
Regarding claim 2, Chen discloses all of the limitations of claim 1, and further discloses that etching the fin structure to a first depth is performed continuously (Chen paragraph 0041. The etch can be a single etch, which would mean there are no breaks, which would make it continuous).
Regarding claim 3, Chen discloses all of the limitations of claim 2, and further discloses that the first depth is below the source/drain regions (Chen paragraph 0047).
Regarding claim 4, Chen discloses all of the limitations of claim 1, and further discloses that depositing the enhanced passivation layer comprises performing an atomic layer deposition process (Chen paragraph 0049).
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Claims 21 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhu (US 20210013105 A1), hereinafter referred to as "Zhu".
Regarding claim 21, Zhu discloses a method, comprising: forming a fin structure (F in Zhu figure 19) extending along a first direction (left and right in figure 19) on a semiconductor substrate (1002/1002-1 in figure 19); forming a gate structure (1040 in figure 19) extending along a second direction and disposed across the fin structure (extends into and out of the page and on the fins F); forming a first source/drain region and a second source/drain region on the fin structure and on opposite sides of the gate structure (source/drain regions 1032 are on the fins and on either side of each gate); and forming an isolation structure in the gate structure (1048 in figure 19), wherein the isolation structure extends from a top surface of the fin structure into the semiconductor substrate (see figure 19), the isolation structure has a maximum width at a first level below the first and second source/drain regions (wide section of the isolation feature in the substrate part of figure 19), and a necking width at a second level between the first level and the top surface of the fin structure (thinner part of the isolation feature in the fin/gate part of figure 19).
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Regarding claim 22, Zhu discloses all of the limitations of claim 21 (see 112(b) rejection above), and further discloses forming a passivation layer on sidewalls of the isolation structure (dielectric 1046 on the sidewalls of the trench, labeled in figure 18), wherein the passivation layer is disposed above the first level (it is disposed above the wide part of the isolation feature).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Zhou et al. (US 20190157095 A1), hereinafter referred to as "Zhou".
Regarding claim 5, Chen discloses all of the limitations of claim 4. Chen does not explicitly disclose that etching the fin, depositing the passivation layer, the breakthrough etch, and the second etch of the fin are all performed in the same chamber. Chen does disclose that each of these etch processes can be plasma etches (Chen paragraphs 0046, 0050, and 0053)
Zhou teaches performing plasma etches and atomic layer deposition in the same chamber (Zhou paragraph 0056). Zhou also teaches that this avoids vacuum breaks when transferring the substrate that can expose the substrate to unwanted materials, atmosphere, and moisture (paragraph 0056).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform all of the etches and the atomic layer deposition of the enhanced passivation layer in the same chamber, like in Zhou, in order to avoid vacuum breaks that could expose the substrate to unwanted materials, atmosphere, and moisture.
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Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Zhu.
Regarding claim 6, Chen discloses all of the limitations of claim 1. Chen does not disclose that the isolation opening has a maximum width between the first and second depth.
Zhu teaches an isolation structure where the isolation opening has a maximum width (wide section of trench T in Zhu figure 18) between the first depth and second depth (wide part is below the first depth of the trench after a first etching step, see Zhou figure 16, and above the second depth of the trench after the second etch). Zhu also teaches that widening the trench like this improves isolation between devices, such as reducing leakage current or short circuits (Zhu paragraph 0089).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to widen the trench of Chen so there is a maximum width between the first and second depths in order to reduce leakage current or short circuit between devices and improve isolation between devices.
Regarding claim 7, Chen in view of Zhu discloses all of the limitations of claim 6. Zhu further discloses that the isolation opening has a minimum width above the first depth (thinner section of trench T in Zhu figure 18, which is above the depth of the first etch). This feature naturally arises from widening the bottom of the trench, as described above in claim 6, and thus is obvious for the same reasons given above.
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Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Wang et al. (US 20230369452 A1), hereinafter referred to as "Wang".
Regarding claim 16, Chen discloses a method comprising: forming a fin structure (24 in figure 10A) on a substrate (20 in figure 10A) along a first direction (into and out of the page), and a first gate structure and a second gate structure across the fin structure (at least 3 gates 48 in figure 10B); depositing a mask layer over the first and second gate structures (52 in Chen figure 10A); forming a pattern in the mask layer (Chen paragraph 0040), wherein the pattern comprises: a first elongated opening formed over and parallel to the first gate structure (see opening 54 in Chen figure 10C); wherein the first elongated opening is shifted from the first gate structure for a first overlay shift (Chen mentions that there can be misalignment in the mask, Chen paragraph 0044, which would be an overlay shift); etching through the first elongated opening in the mask layer to form a first isolation opening in the substrate (Chen figures 11A-15A), wherein the first isolation opening is substantially aligned with the first gate structure (Chen figure 11B, the opening lines up the gate spacers 34, which are aligned with the gate, which makes the opening aligned with the gate); and depositing a dielectric layer to fill the first isolation opening (66 in Chen figure 16A).
Chen only explicitly recites forming one isolation opening.
Wang teaches that multiple gate cut isolation structures can be formed using the same method for each (Wang paragraph 0040, and multiple openings 70 in Wang figure 22). Each isolation structure can help isolate a different part of a semiconductor device, and the additional isolation structures merely perform the same function as one isolation structure, just in a different spot. It has been held that that mere duplication of parts has no patentable significance unless a new and unexpected result is produced (see MPEP 2144.04 VI B). The method steps in Chen used for the first opening can thus be used for this second opening, which would be etching through the second elongated opening in the mask layer to form a second isolation opening in the substrate, and depositing a dielectric layer to fill the second isolation opening.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a second opening for a second isolation structure to isolate some other portion of the device, as in Wang, and to simply use the same processing steps disclosed in Chen to form this second isolation structure.
Regarding claim 17, Chen in view of Wang teaches all of the limitations of claim 16. Chen further discloses that etching through the first and second elongated openings comprises: etching the first gate structure and the second gate structure via the first and second elongated openings to expose the fin structure (Chen figure 11A); and etching through fin structure and into the substrate via the first and second elongated openings to form the first isolation opening and the second isolation opening in the substrate (Chen figures 12A-15A).
Regarding claim 18, Chen in view of Wang teaches all of the limitations of claim 17. Chen further discloses that etching through fin structure and into the substrate comprises: etching the fin structure to a first depth (Chen figure 12A); depositing a passivation layer (62 in Chen figure 13A); performing a breakthrough etch (Chen figure 14A); and etching the fin structure and the substrate to form the first and second isolation openings (Chen figure 15A).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lin and Wang as applied to claim 18 above, and further in view of Zhu.
Regarding claim 19, Chen in view of Wang teaches all of the limitations of claim 18 (see 112(b) rejection above). Chen in view of Lin and Wang does not disclose that the first depth is below a top surface of the substrate.
Zhu discloses an etching process for forming an isolation structure where the depth of the first etching through the fin is below a top surface of the substrate (Zhu figure 16. The trench T goes into the top part of the substrate 1002-1). Zhu further deposits a dielectric to protect sidewalls formed at this stage so that it can be further deepened and widened (Zhu paragraph 0086). That is to say, by etching down deeper into the substrate in the first etch, more of the sidewalls can be protected by the dielectric layer (like the liner 62 in Chen), in service of deepening and widening the trench later. Zhu teaches that deepening and widening the trench like this improves isolation between devices, such as reducing leakage current or short circuits (Zhu paragraph 0089).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention etch the first depth down into the substrate in order to protect more of the sidewalls in order to widen the trench of Chen to reduce leakage current or short circuit between devices and improve isolation between devices, without damaging the rest of the structure of the device.
Regarding claim 20, Chen in view of Wang teaches all of the limitations of claim 18 (see 112(b) rejection above). Chen in view of Lin and Wang does not disclose a second width below the first depth greater than a first width above the first depth.
Zhu teaches an isolation structure where the isolation opening has a first width above the first depth (narrow section of trench T in Zhu figure 18, which is above the depth of the first etch) and a second width below the first depth (wider section of trench T in Zhu figure 18, which is below the depth of the first etch), and the second width is greater than the first depth. Zhu also teaches that widening the trench like this improves isolation between devices, such as reducing leakage current or short circuits (Zhu paragraph 0089).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to widen the trench of Chen in order to reduce leakage current or short circuit between devices and improve isolation between devices.
Claims 24, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu.
Regarding claim 24, Zhu discloses all of the limitations of claim 21 (see 112(b) rejection above). Zhu does not explicitly disclose what the ratio between the maximum width and the necking width is. However, the maximum width is greater than the necking width, since that part of the trench is widened, so the ratio will be greater than 1. Furthermore, Zhu teaches that increasing the width of the bottom of the trench increases it’s isolation properties (Zhu paragraph 0089), which makes the maximum width a result effective variable. One of ordinary skill would be motivated to increase the maximum width of the bottom of this trench in order to increase its isolation properties, and would be motivated to not increase it too much, since widening the trench takes manufacturing time.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary the ratio of the maximum width over the necking width through routine optimization (see MPEP 2144.05) in order to arrive at the claimed range of between about 1.5 and about 2.0.
Regarding claim 28, Zhu discloses all of the limitations of claim 21 (see 112(b) rejection above). Zhu does not explicitly disclose that the maximum width is greater than a spacing between the first and second source/drain regions.
Zhu does teach that widening the trench improves isolation between devices, such as reducing leakage current or short circuits (Zhu paragraph 0089). So, one of ordinary skill the art would be motivated to increase the maximum width further in order to further improve the isolation properties of the trench.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to widen the trench of Zhu until it is greater than a spacing between the first and second source/drain regions in order to further reduce leakage current or short circuit between devices and improve isolation between devices.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu in view of Chen and Lo et al. (US 6358859 B1), hereinafter referred to as "Lo".
Regarding claim 23, Zhu discloses all of the limitations of claim 22. Zhu does not explicitly disclose that the passivation layer includes a Br containing silicon oxide.
Zhu discloses that the passivation layer is a dielectric, but only gives two example materials (Zhu paragraph 0086).
Chen teaches dielectric materials that can be used as a passivation layer (liner 62 in Chen) which includes silicon oxide (see Chen paragraph 0049). Since the liner of Chen is used similarly to the dielectric layer 1046 in Zhu, that being to protect the surrounding structure from further etching (Chen paragraph 0054 and Zhu paragraph 0086), using the same material would achieve the same predictable result.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the known material of silicon oxide from Chen as the dielectric in Zhu in order to achieve the predictable result of protecting the surrounding structure from further etching.
For etching the gate and fin down, Zhu does not explicitly disclose what etchants are used, but does say that it can be RIE (Zhu paragraph 0084).
Chen discloses hydrogen bromide as an example etchant for a plasma etch that can be RIE (Chen paragraph 0046). Since both Zhu and Chen are both etching down a fin using RIE, using the etchant of hydrogen bromide would yield the same predictable result of etching down a fin in both cases. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the known technique of etching using hydrogen bromide to the similar device of Zhu in order to achieve the predictable result of etching the fin structure down.
It is known that using hydrogen bromide as an etchant can leave behind residual bromine onto the surfaces being etched (Lo column 1, lines 56-61). Since the dielectric is deposited directly on this surface and exposed to later etches, this would result in it containing bromine.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the hydrogen bromide to etch and the silicon oxide as the dielectric, as in Chen, which would result in a Br containing silicon oxide.
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Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu in view of Ng et al. (US 20210183855 A1), hereinafter referred to as "Ng".
Regarding claim 25, Zhu discloses all of the limitations of claim 21 (see 112(b) rejection above), where the second level is below the entire fin structure. Zhu does not disclose that the fin structure comprises two or more semiconductor channel layers vertically stacked.
Ng teaches a fin structure that comprises two or more semiconductor channel layers vertically stacked (fin 118 has stacked semiconductor layers 110 in Ng figure 1). Ng also teaches that these gate-all around devices allow the devices to be scaled down while maintaining gate control.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the stacked semiconductor layers of Ng in order to scale down the device while maintaining gate control.
Furthermore, since the second level in Zhu is below the entire fin structure, and the stacked layers of Ng are all part of the fin structure, the resulting combined method would have that the second level is below a bottom most semiconductor channel layer.
Claims 26 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu in view of Lin et al. (US 20220052175 A1), hereinafter referred to as "Lin".
Regarding claim 26, Zhu discloses all of the limitations of claim 21 (see 112(b) rejection above). Zhu does not explicitly disclose that the isolation structure has any overlay shift.
Lin teaches that overlay shifts can occur from errors in the accuracy of photolithography operations, especially as device get smaller (Lin paragraph 0005). Naturally, not every photolithography step will be perfect, and thus the method can include some overlay shift.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the isolation structure can have a first overlay shift relative to the gate structure above a top surface of the fin structure, and a second overlay shift relative to the gate structure at the first level.
Regarding claim 27, Zhu in view of Lin discloses all of the limitations of claim 26. Zhu does not explicitly recite that the first overlay shift is greater than the second.
The method of Zhu does disclose depositing a dielectric layer 1046 on sidewalls of the trench which suppresses influences on the profile of the sidewalls, and narrows the trench at that part. This will naturally protect the lower regions of the trench more from the effects of any misalignment in the mask more than the upper regions of the trench, since the lower regions will have protection for more of the etching time, and will functionally have a narrower mask when considering the dielectric layer. This would result in the first overlay shift being greater than the second overlay shift. In addition, since Zhu’s method is essentially the same as the method being claimed, one would expect to see the same effects to result from it.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 16, 17, 18, and 20 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 18, 18, 19, and 20, respectively, of copending Application No. 19/294,473 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the reference application anticipate the claims of the instant application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Regarding claims 16-18 and 20, see chart below:
Claim#
Instant Application (18/646,964)
Claim#
Reference Application (19/294,473)
16
A method comprising:
forming a fin structure on a substrate along a first direction, [1]
and a first gate structure and a second gate structure across the fin structure; [2]
depositing a mask layer over the first and second gate structures; [3]
forming a pattern in the mask layer, [4]
wherein the pattern comprises: a first elongated opening formed over and parallel to the first gate structure, [5]
wherein the first elongated opening is shifted from the first gate structure for a first overlay shift; [6]
and a second elongated opening formed over and parallel to the second gate structure; [7]
etching through the first and second elongated openings in the mask layer to form a first isolation opening and a second isolation opening in the substrate, [8]
wherein the first isolation opening is substantially aligned with the first gate structure; [9]
and depositing a dielectric layer to fill the first isolation opening and the second isolation opening. [10]
18
A method (100a) (100) comprising:
forming a device comprising: a fin structure on a substrate (210) along a first direction, [1]
wherein the fin structure comprises a well portion (212) extending from the substrate (210) and a channel portion disposed on over the well portion (212);
a first gate structure across the fin structure; and a second gate structure across the fin structure; [2]
depositing a mask layer (254) (248) over the first and second gate structures; [3]
forming a pattern in the mask layer (254) (248), [4]
wherein the pattern comprises: a first elongated opening (262) (260) formed over and parallel to the first gate structure, [5]
wherein the first elongated opening (262) (260) is shifted from the first gate structure for a first overlay shift; [6]
and a second elongated opening (262) (260) formed over and parallel to the second gate structure; [7]
etching the first gate structure and the second gate structure via the first and second elongated openings (256c) (256b) (256) to expose the well portion (212) of the fin structure; [11]
etching through the well portion (212) and into the substrate (210) via the first and second elongated openings (256c) (256b) (256) to form ta first isolation opening (262) (260) and a second isolation opening (262) (260) in the substrate (210), [8], [12]
wherein the first isolation opening (262) (260) is substantially aligned with the first gate structure; [9]
and depositing a dielectric layer (254) to fill the first isolation opening (262) (260) and the second isolation opening (262) (260). [10]
17
The method of claim 16, [1-10]
wherein etching through the first and second elongated openings comprises: etching the first gate structure and the second gate structure via the first and second elongated openings to expose the fin structure; [11]
and etching through fin structure and into the substrate via the first and second elongated openings to form the first isolation opening and the second isolation opening in the substrate. [12]
18
The method of claim 17, [1-12]
wherein etching through fin structure and into the substrate comprises: etching the fin structure to a first depth; [13]
depositing a passivation layer; [14] performing a breakthrough etch; [15]
and etching the fin structure and the substrate to form the first and second isolation openings. [16]
19
The method of claim 18, [1-12]
wherein etching through well portion and into the substrate comprises: etching the well portion to a first depth; [13]
depositing a passivation layer; [14]
performing a breakthrough etch; [15]
and etching the well portion and the substrate to form the first and second isolation openings. [16]
20
The method of claim 17, [1-12]
wherein the first isolation opening has a first width above the first depth and a second width below the first depth, and the second width is greater than the first depth. [17]
20
The method of claim 19, [1-16]
wherein the first isolation opening has a first width above the first depth and a second width below the first depth, and the second width is greater than the first depth. [17]
Note that since the well portion is part of the fin, any etch of the well portion is an etch of the fin.
Claims 1-7 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-8, respectively, of copending Application No. 19/294,473 in view of Chen.
This is a provisional nonstatutory double patenting rejection.
Regarding claims 1-7, see chart below:
Claim#
Instant Application (18/646,964)
Claim#
Reference Application (19/294,473)
1
A method comprising:
forming a fin structure on a substrate along a first direction, [1]
a gate structure across the fin structure, [2]
and source/drain regions on opposite sides of the gate structure; [3]
depositing a mask layer over the gate structure; [4]
forming a pattern in the mask layer, [5]
wherein the pattern comprises an elongated opening formed over a portion of the gate structure; [6] and
etching the gate structure through the elongated opening to expose the fin structure; [7]
etching the fin structure to a first depth; [8]
depositing an enhanced passivation layer; [9]
performing a break-through etch process; and [10]
etching the fin structure and the substrate to a second depth to form an isolation opening; [11] and
filling the isolation opening with a dielectric material. [12]
1
A method, comprising:
forming a device comprising: a fin structure on a substrate along a first direction, [1]
wherein the fin structure comprises a well portion extending from the substrate and a channel portion disposed on over the well portion;
a gate structure across the fin structure; [2]
source/drain regions on opposite sides of the gate structure [3]
and connected with the channel portion; and gate sidewall spacers on between the gate structure and the source/drain regions;
depositing a mask layer over the gate structure; [4]
forming a pattern in the mask layer, [5]
wherein the pattern comprises an elongated opening formed over a portion of the gate structure; and [6]
forming an isolation opening by one or more etching processes through the elongated opening, wherein the isolation opening between the gate sidewall spacers, through the channel portion and into the well portion, wherein the isolation opening has a maximum width along the first direction at the well portion of the fin structure;
and filling the isolation opening with a dielectric material. [12]
2
The method of claim 1, [1-6] and [12]
wherein forming the isolation opening comprises: etching the fin structure to a first depth; [8]
depositing an enhanced passivation layer; [9]
performing a break-through etch process; and [10]
etching the fin structure and the substrate to a second depth. [11]
2
The method of claim 1, [1-12]
wherein etching the fin structure to a first depth is performed continuously. [13]
3
The method of claim 2, [1-6] & [8-12]
wherein etching the fin structure to a first depth is performed continuously. [13]
3
The method of claim 2, [1-13]
wherein the first depth is below the source/drain regions. [14]
4
The method of claim 3, [1-6] & [8-13]
wherein the first depth is below the source/drain regions. [14]
4
The method of claim 1, [1-12]
wherein depositing the enhanced passivation layer comprises performing an atomic layer deposition process. [15]
5
The method of claim 2, [1-6] & [8-12]
wherein depositing the enhanced passivation layer comprises performing an atomic layer deposition process. [15]
5
The method of claim 4, [1-12] & [15]
wherein etching the fin structure to a first depth, depositing the enhanced passivation layer, performing a break through etch process, and etching the fin structure and the substrate to a second depth are performed in the same chamber. [16]
6
The method of claim 5, [1-6], [8-12] & [15]
wherein etching the fin structure to a first depth, depositing the enhanced passivation layer, performing a break through etch process, and etching the fin structure and the substrate to a second depth are performed in a same chamber. [16]
6
The method of claim 1, [1-12]
wherein the isolation opening has a maximum width between the first depth and second depth. [17]
7
The method of claim 2, [1-6] & [8-12]
wherein the maximum width of the isolation opening is between the first depth and second depth. [17]
7
The method of claim 6, [1-12] & [17]
wherein the isolation opening has a minimum width above the first depth. [18]
8
The method of claim 7, [1-6], [8-12] & [17]
wherein the isolation opening has a minimum width above the first depth. [18]
Note that since the well portion is part of the fin, any etch of the well portion is an etch of the fin. The claims of the reference application anticipate the claims of the instant application with the exception of the limitation [7]: “etching the gate structure through the elongated opening to expose the fin structure”. The reference claims do not explicitly recite etching the gate structure. Chen teaches etching the gate structure through the elongated opening to expose the fin structure (Chen figure 11A). This step removes the gate from that section and allows the fin underneath to be etched to further create the isolation structure. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to etch the gate structure through the elongated opening in order to later etch the fins underneath and create the isolation opening.
Conclusion
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/DANIEL KURT ELLIOTT/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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