Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/26/2024 is being considered by the examiner.
Claim Rejections - 35 USC § 112
Claim16 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation "the second electrode" in its body. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2,4-6,8-12,14, is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al, US 20230215896 A1.
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Pertaining to claim 1, Lee teaches ( see fig.3 above) A packaged chip[100], comprising: a base material [1] comprising a first electrode[13]; a chip disposed[2] on the base material[1] and electrically connected with the first electrode[13]; and a packaging layer[combination of elements 6/7/5] disposed on the base material[1] and surrounding the chip[2], wherein the base material[1] comprises a surface, a first distance[23/M] is between a top surface of the chip[2] and the surface of the base material[1], the surface of the base material [1]comprises a coupling portion[14], and in a cross-sectional direction, a height or a depth of the coupling portion [14] is less than the first distance[23/M].
Pertaining to claim 2, Lee teaches ( see fig.3 above) The packaged chip as claimed in claim 1, wherein the coupling portion[14] is a protrusion ( see para [0027), a recess, or a combination thereof.
Pertaining to claim 4, Lee teaches ( see fig.3 above) The packaged chip as claimed in claim 1, wherein the coupling portion[14] is disposed on an edge of the base material[1].
Pertaining to claim 5, Lee teaches ( see fig.5) The packaged chip as claimed in claim 1, wherein in a top view direction, the coupling portion [14] surrounds the chip [2].
Pertaining to claim 6, Lee teaches ( see fig.7) The packaged chip as claimed in claim 1, wherein the base material[1] further comprises an island portion[111/112]], the coupling portion[14] surrounds the island portion[111/112] in the cross-sectional direction, and the chip[2] is disposed on the island portion[111/112].
Pertaining to claim 8, Lee teaches ( see fig.4 for example) The packaged chip as claimed in claim 1, wherein in a top view direction, the chip[2] is spaced a second distance from an edge of the base material[1], the coupling portion( see the last coupling portion 14 near the edge of the base [1] is spaced a third distance from the edge of the base material[1], and the third distance is less than or equal to half of the second distance( by the virtue of the fig.4).
Pertaining to claim 9, Lee teaches ( see fig.4 for example). The packaged chip as claimed in claim 1, wherein in the cross-sectional direction, the height or the depth of the coupling portion [14] is less than half of the first distance[23/M] ( by virtue of the shape of figure 3).
Pertaining to claim 10, Lee teaches ( see figs.3 and 4 The packaged chip as claimed in claim 1, wherein in a top view direction, the coupling portion[14] comprises a plurality of sub-coupling portions( see plurality of protruding element 14 from fig4), and the plurality of sub-coupling portions discontinuously surrounds the chip[2], wherein a corner of the chip[2] corresponds to a gap between two adjacent sub-coupling portions of the plurality of sub-coupling portions[14].
Pertaining to claim 11, Lee teaches ( see fig.3 and 4above) The packaged chip as claimed in claim 10, wherein the two adjacent sub-coupling portions[14] are respectively disposed on two adjacent sides of the chip[2].
Pertaining to claim 12, Lee teaches ( see fig.3 above) The packaged chip as claimed in claim 1, wherein the coupling portion[14] is a protrusion, and the coupling portion [14] has an arc top profile.
Pertaining to claim 14, Lee teaches ( see fig.4) The packaged chip as claimed in claim 1, wherein the coupling portion[14] comprises: a first sub-coupling portion(first rectangular shape of element 14 around the chip2) surrounding the chip[2]; and a second sub-coupling portion( second rectangular shape of element 14 around the chip2) surrounding the first sub-coupling portion.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kong et al, US 20180031759 A1 in view Lee et al, US 20230215896 A1
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Pertaining to claim 18, Kong teaches ( see fig.5 of Kong above ) A backlight module, comprising: a substrate[125]; and a plurality of packaged chips[127] disposed on the substrate[125],
But is silent wherein at least one of the plurality of packaged chips comprises: a base material comprising a first electrode; a chip disposed on the base material and electrically connected with the first electrode; and a packaging layer disposed on the base material and surrounding the chip, wherein the base material comprises a surface, a first distance is between a top surface of the chip and the surface of the base material, the surface of the base material comprises a coupling portion, and in a cross-sectional direction, a height or a depth of the coupling portion is less than the first distance.
However, in the same field of endeavor Lee teaches ( see fig.3 of Lee above) wherein at least one of the packaged chip [100] comprises comprising: a base material [1] comprising a first electrode[13]; a chip disposed[2] on the base material[1] and electrically connected with the first electrode[13]; and a packaging layer[combination of elements 6/7/5] disposed on the base material[1] and surrounding the chip[2], wherein the base material[1] comprises a surface, a first distance[23/M] is between a top surface of the chip[2] and the surface of the base material[1], the surface of the base material [1]comprises a coupling portion[14], and in a cross-sectional direction, a height or a depth of the coupling portion [14] is less than the first distance[23/M].
In view of Lee , it would have been obvious to one of ordinary skill in the art to incorporate some of the design structure of the chip packaging of Lee into the plurality of the chips of the backlight module of Kong so that the contact area and connection strength between the substrate and the ring-shaped wall can be effectively increased, and the protrusions can lengthen a traveling path of moisture that is defined along the connection interface between the substrate and the ring-shaped wall ( see para 0007 of Lee)
Pertaining to claim 19, Kong teaches ( see fig.5 of Kong above The backlight module as claimed in claim 18, further comprising: an optical film ( see para 0055) disposed on the plurality of packaged chips[127].
Pertaining to claim 20, Kong teaches ( see fig.5 of Kong above )The backlight module as claimed in claim 18, further comprising: a plurality of reflective layers[128/320,126], wherein each of the plurality of reflective layers is disposed on a respective packaged chip[127].
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20230215896 A1 in view of INODA et al, US 20240309158 A1.
Pertaining to claim 15, Lee teaches ( see fig.4) the packaged chip as claimed in claim 1, but is silent wherein the packaging layer comprises: a packaging matrix; and dispersed particles dispersed in the packaging matrix.
However, in the same field of endeavor , INODA teaches wherein a packaging layer comprises: a packaging matrix; and dispersed particles dispersed in the packaging matrix ( see abstract or para 0012). In view of INODA , it would have been obvious to one of ordinary skill in the art to incorporate this packaging layer into that of Lee for an excellent folding endurance, and also excellent low-temperature heat sealing property.
Claim(s) 3 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20230215896 A1 in view of Chen et al, US 20200274039 A1.
Pertaining to claims 3 and 16, Lee teaches ( see fig.4) the packaged chip as claimed in claim 1, but it did not specifically teach wherein the chip comprises a second electrode, and wherein the second electrode overlaps the first electrode and is electrically connected to the first electrode and to further comprising: a bonding element disposed between the first electrode and the second electrode and electrically connected to the first electrode and the second electrode.
However, in the same field of endeavor , Chen teaches ( see fig.17 of Chen for example) comprising: wherein the chip comprises a second electrode[138-1], and wherein the second electrode overlaps the first electrode[122] and is electrically connected to the first electrode[122] , a bonding element [BE] disposed between the first electrode[122] and the second electrode [138-1]and electrically connected to the first electrode and the second electrode.
In view of Chen , it would have been obvious to one of ordinary skill in the art to incorporate this structure contact design into that of Lee for a simplify bonding structure and more compact packaging structure.
Pertaining to claim 17, Lee teaches ( see fig.4) the packaged chip as claimed in claim 1, but it did not specifically teach wherein the coupling portion [14]surrounds at least two chips.
However, in the same field of endeavor , Chen teaches ( see fig.17 of Chen for example) at least two chip in the package structure.
In view of Chen , it would have been obvious to one of ordinary skill in the art to substitute the multiple chips of Chen into that of Lee with the coupling portion with still an improved sealing structure
Allowable Subject Matter
Claims 7,13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The closest prior art of record of Lee et al, US 20230215896 A1) teaches the limitation of claim1, but does not teach or suggest, singularly or in combination, at least the limitations of the independent claim 7 including “further comprising: an air gap located between the coupling portion and the packaging layer.” in combination with the remaining limitations of the claim.
it does not also teach or suggest, singularly or in combination, at least the limitations of the independent claim 13 including “wherein the coupling portion is a recess, and the coupling portion has a tip bottom profile.” in combination with the remaining limitations of the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
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/MAMADOU L DIALLO/Primary Examiner, Art Unit 2897
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