DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 26, 2024 is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “different of the transistor-material tiers” in line 10. It is unclear what difference is identified by this limitation. This will be interpreted as “different transistor-material tiers”
Claim 10 recites “different of the transistor-material tiers” in line 10. It is unclear what difference is identified by this limitation. This will be interpreted as “different transistor-material tiers”
Claim 14 recites “different of the transistor-material tiers” in line 10. It is unclear what difference is identified by this limitation. This will be interpreted as “different transistor-material tiers”
Claim 19 recites “different of the transistor-material tiers” in line 10. It is unclear what difference is identified by this limitation. This will be interpreted as “different transistor-material tiers”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-7, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2013/0153851) in view of Kajigaya (US 2013/0070506). Claim 1, Park discloses (Figs. 1-2, 9, and 18) a method of forming a memory array (Fig. 18, 1000, memory device, Para [0044]), the memory array comprising memory cells individually comprising a transistor (Tr, transistor, Para [0046]) and a resistor (Rv, variable resistor, Para [0046]), the method comprising: forming (Figs. 1 and 2) vertically-alternating tiers of insulative material (115, interlayer insulating layer, Para [0031]) and transistor material (110, active layer, Para [0031]); the transistor-material tiers (110) individually comprising a first source/drain region (Fig. 1, S, source, Para [0038]) and a second source/drain region (D, drain, Para [0038]) having a channel region horizontally there-between (region between S and D in x-direction and extending in z-direction considered channel region, hereinafter “channel”); forming (Figs. 1 and 9) a pair of access-line pillars ( pair of 157 and G lateral spaced apart in x-direction, conductive pillar, Para [0042], hereinafter “access”) extending elevationally through the vertically-alternating tiers on opposite sides of individual ones of the channel regions (access extends through 115/110 on either side of channel) that are in different transistor-material tiers (different pairs of 115/110), portions of the access-line pillars in the different transistor-material tiers comprising a pair (fig. 1 shows pair of G for example) of gates (G, gate electrode, Para [0024]) on the opposite sides of the individual ones of the channel regions of individual ones of the transistors in the different transistor-material tiers (portions of G surround opposite sides of channel in each individual transistor comprising S/D/G as shown in Fig. 1); forming a sense line (Fig. 1, (120, bit line, Para [0026]) electrically coupled to multiple of the second source/drain regions (120 coupled to various S and D regions, Para [0026]). Park does not disclose a capacitor; and forming capacitors individually comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to individual ones of the first source/drain regions, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another.
However, Kajigaya discloses (12A-13) a capacitor (60/61/NS form capacitors, Para [0076], hereinafter “capacitor”) comprising first (NS, storage node, Para [0077]) and second electrodes (60, common electrode, Para [0077]) having a capacitor insulator (61, high-dielectric constant insulating film, Para [0077]) there-between (61 between NS and 60), the first electrode being electrically coupled to the first source/drain region (Fig. 13, NS is coupled to a source/drain region of the circuit diagram in Fig. 13),
the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another (60 is common to the capacitors, Para [0077]); Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the capacitor structure of Kajigaya as it a substitution of known alternatives for the resistors of Park (Kajigaya, Para [0044]), re Ruff, 256 F.2d 590, 118 USPQ 340, see MPEP 2144.06 II.
Claim 2, Park in view of Kajigaya discloses the method of claim 1. Park discloses (Figs. 1-2, 9, and 18) comprising forming conductor material (Fig. 1, 160, word line, Para [0042]) that directly electrically couples the pair of access-line pillars together (160 couples access as shown in Fig. 1). Claim 3, Park in view of Kajigaya discloses the method of claim 2. Park discloses (Figs. 1-2, 9, and 18) comprising forming the conductor material (160) above the pair of access-line pillars (160 is above access). Claim 5, Park in view of Kajigaya discloses the method of claim 1. Park discloses (Figs. 1-2, 9, and 18) wherein the channel region (channel) is on only one side of individual ones of the gates in a straight-line horizontal cross-section (as can be seen in Fig. 9 cross-section, channel is only on one side of individual G). Claim 6, Park in view of Kajigaya discloses the method of claim 1. Park discloses (Figs. 1-2, 9, and 18) wherein the access-line pillars (access) extend vertically or within 10° of vertical (access extends vertically as seen in Fig. 1). Claim 7, Park in view of Kajigaya discloses the method of claim 1. Park discloses (Figs. 1-2, 9, and 18) wherein all of the channel region (channel) is horizontally-oriented for horizontal current flow there-through (Fig. 1 shows channel is oriented in horizontal x direction for horizontal current flow). Claim 9, Park in view of Kajigaya discloses the method of claim 1. Park discloses (Figs. 1-2, 9, and 18) wherein individual ones of the multiple second source/drain regions (D) are directly electrically coupled to the sense line (D are coupled to 120).
Allowable Subject Matter
Claims 4 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the 112 rejection above and in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Park (US 2013/0153851), Kajigaya (US 2013/0070506), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 4, forming a horizontal longitudinally-elongated conductive line above and directly electrically coupled to the conductor material of multiple of the pairs of access-line pillars.
Regarding Claim 8, wherein the first electrode is directly electrically coupled to the first source/drain region.
Claims 10-20 would be allowed if rewritten to overcome the 112 rejection above.
Regarding Claim 10 (from which claims 11-13 depend), forming the first and second source/drain regions to each have a vertical side that is directly against both of the channel region and the gate insulator, a greater quantity of each of the vertical sides of the first and second source/drain regions being directly against the gate insulator than is directly against the channel region…
Regarding Claim 14 (from which claims 15-18 depend), forming two conductive lines that are longitudinally-elongated along an x-direction that is orthogonal to the y-direction, one of the two conductive lines directly electrically coupling together a first series of the conductive straps of multiple of the pairs of access-line pillars that alternate relative to one another along the x-direction, the other of the two conductive lines directly electrically coupling together a second series of the conductive straps of multiple of the pairs of access-line pillars that alternate relative to one another and to the first series of the conductive straps along the x-direction.
Regarding Claim 19 (from which claim 20 depends), forming a conductive line below the conductive line that is above the conductive strap and that is longitudinally-elongated along a y-direction that is orthogonal to the x-direction, the conductive line that is longitudinally-elongated in the y-direction directly electrically coupling together individual ones of the second capacitor electrodes.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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/GUSTAVO G RAMALLO/Examiner, Art Unit 2812
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