Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 02/19/2026 have been fully considered but they are not persuasive.
Applicant argues, in substance, that Na et al. operates in the current domain rather than the voltage domain and therefore does not disclose a multiplexer configured to select a test voltage or an ADC configured to provide a digital output based on comparing the test voltage with a reference voltage. Applicant further relies on the incorporation of the subject matter of former claim 4 into independent claims 1 and 17 and corresponding conductive-structure subject matter into independent claim 9.
The Examiner respectfully disagrees. Under the broadest reasonable interpretation consistent with the Specification, the claims do not require the signal selected by the multiplexer to exist exclusively as a voltage signal throughout the entire sensing and conversion path. Na et al. discloses a resistive stress detector to which a voltage is applied and through which a corresponding sensing current flows. Na et al. expressly provides that sensing current SI1 is related to the voltage difference and resistance according to SI1=(VDD−VREF)/R (paragraph [0123]). Thus, characterization of the selected electrical signal as a sensing current does not negate the voltage necessarily present in the resistive sensing path. Na et al. also expressly discloses voltage comparison within ADC 620. Specifically, operational amplifier 645 compares the voltage at node N14 with reference voltage VREF as part of generating the digital stress index code (paragraph [0120]). Accordingly, Applicant’s argument that Na et al. performs only current-domain conversion and does not use voltage comparison is not persuasive.
The Examiner has also reconsidered the previous indication that former dependent claim 4 contained allowable subject matter. The limitation incorporated into amended claims 1 and 17 recites that the conductive structures comprise “at least one of” TSVs, SPRs, a uBump, a hybrid bond, or an interconnect structure between dies. This language recites alternative structures. Therefore, the prior art need only teach or suggest one of the recited alternatives and need not disclose every listed structure.
Chen et al. expressly teaches conductive interconnect structures associated with bonded semiconductor structures. For example, Chen et al. discloses a BEOL structure including interconnected conductive structures electrically connected through conductive vias to semiconductor devices (paragraph [0027]). Chen et al. therefore supplies the conductive interconnect structure that Na et al. does not expressly identify.
The combination does not change the operating principle of Na et al. Na et al. teaches applying an electrical stimulus to a selected conductive resistive structure, routing the resulting electrical signal, and converting that signal into a digital output. Chen et al. teaches known conductive interconnect structures used in bonded semiconductor devices. Applying Na et al.’s electrical sensing arrangement to the interconnect structures of Chen et al. would have been a predictable application of known sensing circuitry to known conductive semiconductor structures.
Accordingly, the previous indication of allowable subject matter in former claim 4 has been reconsidered and withdrawn in view of the additional prior art and the breadth of the alternative limitation. Applicant’s amendments do not overcome the rejection because Chen et al. teaches at least the broadly recited “interconnect structure between dies” alternative.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 & 5-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Na et al. (U.S. 2020/0105308 A1, previously cited) in view of Chen et al. (U.S. 2022/0359459 A1, newly cited).
Regarding claim 1, Na teaches a circuit as seen in Figs. 6 & 18 comprising: a signal source configured to provide a test signal to at least one of a plurality of conductive structures based on a decoded signal (external voltage VPPx is selectively supplied to stress detectors SDT1–SDT6 through power switch PSW and switches SW1–SW6 in response to control signals; paragraph [0108]); a plurality of switches configured to connect the signal source to the plurality of conductive structures, respectively, based on the decoded signal (switches SW1–SW6 are sequentially activated to provide external voltage VPPx to corresponding stress detectors SDT1–SDT6; paragraph [0108]); a multiplexer configured to select a test voltage present on the at least one conductive structure, based on the decoded signal (multiplexer 610 selects a sensing signal associated with one of stress detectors SDT1–SDTq in response to selection signal SS; paragraph [0113]); and an analog-to-digital converter configured to provide a digital output based on comparing the test voltage with a reference voltage (operational amplifier 645 compares the voltage at node N14 with reference voltage VREF as part of generating stress index code SIC1; paragraph [0120]; wherein under the broadest reasonable interpretation, the electrical signal selected from the resistive stress detector includes the voltage present in the selected resistive measurement path. Na expressly relates the selected sensing current to the applied voltage difference and resistance according to SI1=(VDD−VREF)/R (paragraph [0123]). The claim does not require the multiplexer output to remain exclusively in voltage form throughout the entire signal path).
Na does not expressly teach wherein the plurality of conductive structures comprise at least one of a plurality of TSVs, a plurality of SPRs, a uBump, a hybrid bond, or an interconnect structure between dies.
Chen teaches wherein the plurality of conductive structures comprise an interconnect structure between dies (a wafer includes a BEOL structure having interconnected conductive structures electrically coupled through conductive vias to semiconductor devices; paragraph [0027]; because the claim recites the conductive structures in the alternative, Chen’s disclosure of an interconnect structure is sufficient to satisfy the limitation).
It would have been obvious to one skilled in the art, prior to the effective filing date, to modify Na by incorporating the interconnect structures taught by Chen as the conductive structures subjected to Na’s electrical sensing circuitry, as doing so would provide electrical evaluation of conductive interconnections in bonded semiconductor structures because Chen emphasizes testing semiconductor structures to evaluate electrical performance in paragraph [0053] (also see Na’s {0027], wherein extending Na’s known electrical sensing technique to known conductive interconnect structures).
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As to claim 2, Na et al. in view of Chen et al. disclose the circuit of claim 1, wherein Na et al. further disclose at least one conductive structure comprises a connector structure within one of multiple bonded dies or between two bonded dies (stacked semiconductor package 200a with multiple memory chips CHP1–CHP5 bonded through TSVs and inter-die connections, see Figs. 11–14; [0100]–[0106]).
As to claim 3, Na et al. in view of Chen et al. disclose the circuit of claim 2, wherein Na et al. further disclose ADC is configured to output the digital output during an operation of the bonded dies or the two bonded dies (control circuit 500 controls stress detection during power-on, idle, or wake-up operation of the semiconductor package, see [0142]).
As to claim 5, Na et al. in view of Chen et al. disclose the circuit of claim 1, wherein Na et al. further disclose digital output represents a resistance of the one selected conductive structure (ADC output SIC1 corresponds to resistance R of stress detector SDT where period T1 = nRC, see [0123]–[0124]).
As to claim 6, Na et al. in view of Chen et al. disclose the circuit of claim 1, wherein Na et al. further disclose a decoder connected to the multiplexer and configured to provide the decoded signal (control circuit 500 and signal generator 570 provide selection signal SS and switching control signal SCS to multiplexer 610 and switches SW1–SW6, see [0113]; [0132]).
As to claim 7, Na et al. in view of Chen et al. disclose the circuit of claim 1, wherein Na et al. further disclose a gain component configured to amplify the test voltage and provide an amplified signal to the ADC (ADC 620 includes division current generator 630 and operational amplifiers 645, 655 which amplify the analog input before digital conversion, see Fig. 18; [0115]–[0121]).
As to claim 8, Na et al. in view of Chen et al. disclose the circuit of claim 1, wherein Na et al. further disclose ADC is configured to output the digital output based on a clock signal (ADC 620 implemented as a relaxation oscillator with periodic output SIC1 serving as clock-based digital signal, see [0123]–[0124]).
Regarding claim 9, Na discloses a circuit comprising: a first die and a second die (semiconductor package 200a includes a plurality of memory chips sequentially stacked on a package substrate; [0052]); at least one conductive structure within at least one of the first die or the second die (stress detectors SDT are formed in the substrate of respective memory chips; [0100]); a signal source within one of the first die or the second die (external voltage VPPx is provided through a power switch to the stress detector circuitry; [0108]); at least one switch configured to connect the signal source to the at least one conductive structure through a first conductive path (switch SW1 transfers external voltage VPPx to stress detector SDT; [0110]); and an ADC within the semiconductor circuitry and electrically coupled to the conductive structure for measuring an electrical characteristic thereof (ADC 620 receives the selected sensing signal from stress detector SDT and converts it to stress index code SIC1; [0113]; Under the broadest reasonable interpretation, the claimed first, second, and third “wires” encompass conductive electrical paths connecting the signal source, conductive structure, and ADC. Na’s disclosed conductive paths connecting external voltage VPPx, switch SW1, resistive stress detector RT, and ADC 620 reasonably correspond to such electrical connections).
Na does not expressly teach wherein the at least one conductive structure comprises at least one of a plurality of TSVs, a plurality of SPRs, a uBump, a hybrid bond, or an interconnect structure between the first die and the second die in the claimed arrangement.
Chen teaches an interconnect structure between first and second semiconductor structures, wherein a first wafer includes a BEOL interconnected structure electrically connected through conductive vias (see [0027]). Chen also teaches a TSV 608 electrically connecting hybrid bonding structure 50 to another conductive test structure ([0049]; the conductive structures in the alternative, Chen’s disclosure of an interconnect structure and/or TSV satisfies at least one of the expressly recited alternatives).
It would have been obvious to one skilled in the art, prior to the effective filing date, to modify Na by incorporating the inter-die conductive interconnect structures taught by Chen as the structures subjected to Na’s electrical sensing circuitry, as doing so would permit electrical characteristics of conductive paths in bonded semiconductor structures to be evaluated because Chen emphasizes electrical testing of semiconductor devices associated with wafer bonding to evaluate device quality and electrical performance ([0053]), thus predictably applying Na’s known sensing circuitry to known conductive interconnect structures in bonded semiconductor devices.
As to claim 10, Na et al. & Chen et al. disclose the circuit of claim 9, wherein Na et al. further disclose a multiplexer configured to connect the at least one conductive structure and the ADC (see ADC 620 comprising division current generator 630, operational amplifiers 645 and 655, and current mirror circuits that adjust and amplify analog input signals prior to digital conversion).
As to claim 11, Na et al. & Chen et al. disclose the circuit of claim 9, wherein Na et al. further disclose further comprising a gain component configured to connect the at least one conductive structure and the ADC (ADC 620 comprising division current generator 630, operational amplifiers 645 and 655, and current mirror circuits that adjust and amplify analog input signals prior to digital conversion, Fig. 18; [0115]–[0121]; the Examiner regards these amplification circuits within the ADC as the claimed gain component providing signal amplification to the ADC input).
As to claim 12, Na et al. & Chen et al. disclose the circuit of claim 9, wherein Na et al. further disclose a resistor connecting the analog-to-digital converter to a second end of the at least one conductive structure (see sensing current SI1 passes through a path including stress detectors SDT functioning as resistive elements between the conductive structure and ADC input, [0113]–[0118]; the Examiner considers the resistive characteristics of the stress detector or sensing path equivalent to the claimed resistor electrically connecting the ADC to the conductive structure).
As to claim 13, Na et al. & Chen et al. disclose the circuit of claim 9, wherein Na et al. further disclose the ADC comprises a sigma delta ADC (see switches SW1–SW6 are sequentially driven by control signal SCS and multiplexer 610 directs each sensing current SI1–SIq into ADC 620 for conversion, Fig. 15; [0108]; [0113]; the Examiner determines that the sequential conversion of signals from multiple conductive structures inherently yields a sequence of digital outputs as recited).
As to claim 14, Na et al. & Chen et al. disclose the circuit of claim 9, wherein Na et al. further disclose a first terminal to provide an input signal to the at least one conductive structure (see [0101]), and a second terminal to receive an output of the at least one conductive structure (see stacked semiconductor package 200a with multiple memory chips CHP1–CHP5 bonded through TSVs and inter-die connections, see Figs. 11–14; [0104 & 0106]).
As to claim 15, Na et al. & Chen et al. disclose the circuit of claim 9, wherein Na et al. further disclose the first die and the second die are arranged face to face or face to back (see Fig. 7 and [0068]; wherein die are arranged face to face)
As to claim 16, Na et al. & Chen et al. disclose the circuit of claim 15, wherein Na et al. further disclose the first die and the second die are arranged face-to-face or face-to-back (see Fig. 9, wherein vertically stacked semiconductor dies interconnected, see [0068 & 0076]).
Regarding claim 17, Na discloses a method comprising: providing, by a signal source, a test signal to at least one of a plurality of conductive structures based on a decoded signal (external voltage VPPx is selectively applied to stress detectors SDT through switches SW1-SW6; [0108]); connecting, by a plurality of switches, the signal source to the plurality of conductive structures, respectively, based on the decoded signal (switches SW1-SW6 are sequentially turned on in response to switching control signal SCS; [0108]); selecting, by a multiplexer, a test voltage present on the at least one conductive structure, based on the decoded signal (multiplexer 610 selects one sensing signal associated with one of stress detectors SDT1-SDTq in response to selection signal SS; [0113]); and providing, by an ADC, a digital signal based on comparing the test voltage with a reference voltage (operational amplifier 645 compares reference voltage VREF with the voltage of node N14 as part of ADC code generation; [0120]; under the broadest reasonable interpretation, Na’s selected sensing signal is generated from a resistive conductive structure having a voltage applied thereto, and the resulting electrical signal is subjected to voltage comparison against VREF within ADC 620. Therefore, the fact that Na describes the selected signal as sensing current SI1 does not exclude the presence and use of a corresponding test voltage in the disclosed electrical measurement operation).
Na does not expressly teach wherein the plurality of conductive structures comprise at least one of a plurality of TSVs, a plurality of SPRs, a uBump, a hybrid bond, or an interconnect structure between dies.
Chen teaches an interconnected structure within a BEOL structure electrically connected through conductive vias (see [0027]). Chen additionally teaches TSV 608 electrically connected to hybrid bonding structure 50 (see [0049] wherein at least one of the alternatively recited conductive structures).
It would have been obvious to one skilled in the art, prior to the effective filing date, to modify Na’s method by performing Na’s electrical sensing and conversion operations on the interconnect structures taught by Chen, as doing so would permit electrical evaluation of conductive interconnections associated with bonded semiconductor structures because Chen emphasizes electrical testing for evaluating semiconductor device performance in connection with wafer bonding (see [0053]), thus providing a predictable use of Na’s known electrical measurement method for testing known semiconductor interconnect structures).
As to claim 18, Na et al. & Chen et al. disclose the method of claim 17, wherein Na et al. further disclose amplifying, by a gain component, the test voltage (ADC 620 includes operational amplifiers 645, 655 and current mirror 630 acting as gain components, see [0115] & [0121]).
As to claim 19, Na et al. & Chen et al. disclose the method of claim 17, wherein Na et al. further disclose digital signal represents a resistance of the one selected conductive structure (stress index code SIC1 corresponds to resistance R of stress detector SDT, see [0123]–[0124]).
As to claim 20, Na et al. & Chen et al. disclose the method of claim 17, wherein Na et al. further disclose outputting the signal during an operation of the plurality of conductive structures (control circuit 500 detects and outputs stress index codes SIC during power-on or idle operation of semiconductor package, see [0142]).
Regarding claim 21, Na et al. & Chen et al. discloses the circuit of claim 9, wherein Na et al. further disclose the ADC is configured to provide a digital output based on comparing a test voltage with a reference voltage (first operational amplifier 645 compares reference voltage VREF with the voltage at node N14 and provides a comparison output used by the code generation circuit to generate digital stress index code SIC1; [0120]; under the broadest reasonable interpretation, the voltage at node N14 is a test-related voltage resulting from the electrical measurement path originating at the selected resistive conductive structure. however, it does not require the “test voltage” to remain unchanged from the conductive structure to the comparison input, nor does it exclude intermediate current mirroring or signal conditioning. Na’s ADC therefore provides its digital output based on a voltage comparison between the test-related node voltage and reference voltage VREF as claimed).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. 2021/0190854 A1 to Oh et al. disclose a semiconductor device includes a forcing line extending in a first direction over a through-electrode, and electrically coupled to the through-electrode; a first monitoring line formed separate from the forcing line by a first interval in a second direction, and extended in the first direction; a second monitoring line formed separate from the forcing line by a second interval in an opposite direction to the second direction, and extended in the first direction; and a selection circuit suitable for outputting a detection signal by selecting any one of a plurality of voltage levels of the first and second monitoring lines according to a monitoring signal.
U.S. 10,943,794 B2 to Fay et al. disclose a semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.
U.S. 2020/0051878 A1 to Seddon discloses methods of making a semiconductor device may include: providing a partial semiconductor wafer. The method may also include providing a wafer holder including a tape portion with one or more openings through the tape portion. The method may include mounting the partial semiconductor wafer over the one or more openings in the tape portion of the wafer holder and providing an electrical connection to the partial semiconductor wafer through the one or more openings in the tape portion during probe test.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRUNG NGUYEN whose telephone number is (571)272-1966. The examiner can normally be reached on Mon- Friday 8AM - 4:00PM Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Examiner: /Trung Q. Nguyen/- Art 2858
/HUY Q PHAN/Supervisory Patent Examiner, Art Unit 2858
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