DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-12 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash et al. (U.S. Patent Application Publication Number 2014/0307514) and Best et al. (U.S. Patent Application Publication Number 2016/0125929).
Regarding Claim 2, Prakash discloses a method comprising:
setting, using a host device (Figure 1, item 12), a first mode (i.e., a read mode) for a memory device (Figure 1, item 14, paragraphs 0053-0054);
receiving, at a data pin (Figure 1, item 22) of the host device, a first signal from the memory device at a first time (paragraph 0054; i.e., a data strobe DQS signal is received);
interpreting, using the host device, the received first signal as a data strobe signal (i.e., a DQS signal) based at least in part on the first mode (paragraph 0054; i.e., the data strobe signal DQS is transmitted from the memory to the host 12 during a read mode);
setting, using the host device, a second mode for the memory device (paragraph 0054; i.e., the “second mode” is when the data strobe gating signal is not asserted so the data strobe signal DQS is not interpreted as received);
receiving, at the data pin of the host device, a second signal from the memory device at a second time (paragraph 0054; i.e., the second signal is the data DQ signal, which may be received at a second time);
interpreting, using the host device, the received second signal as a data signal (paragraph 0054; i.e., the single DQ/DQS line is used to receive both a DQ signal and DQS signal; the host device 12 determines when to interpret the received signal as data [DQ] or strobe [DQS]).
Prakash does not expressly disclose determining, using the host device, a timing relationship between the data strobe signal and an internal clock signal based on interpreting the received first signal as the data strobe signal;
controlling, using the host device, sampling of the data signal using the internal clock signal based at least in part on the determined timing relationship between the data strobe signal and the internal clock signal without the data strobe signal being simultaneously received at the host device.
In the same field of endeavor (e.g., data sampling techniques), Best teaches determining, using the host device (Figure 3, item 50, paragraph 0020; i.e., a memory controller), a timing relationship between the data strobe signal (Figure 3, item DQS) and an internal clock signal (Figure 3, item CLK and Figure 6, item 201, paragraph 0028) based on interpreting the received first signal as the data strobe signal (paragraph 0017);
controlling, using the host device, sampling (Figure 3, item DSS) of the data signal using the internal clock signal based at least in part on the determined timing relationship between the data strobe signal and the internal clock signal without the data strobe signal being simultaneously received at the host device (paragraphs 0017-0018 and 0048; i.e., the adjusted internal clock signal CLK is used instead of the data strobe signal DQS; the data strobe signal is intermittent [not always simultaneously received at the host device]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Best’s teachings of data sampling techniques with the teachings of Prakash, for the purpose of reducing sampling errors and providing a better sampling reference between the host and memory (see Best, paragraphs 0006 and 0023).
Regarding Claim 3, Prakash discloses wherein the first mode comprises a read mode, and interpreting the received second signal as a data signal is based at least in part on the read mode (paragraphs 0053-0054; i.e., read data is sent from the memory device to the host in a read mode).
Regarding Claim 4, Prakash discloses wherein the second mode comprises a calibration mode, and interpreting the received first signal as a data strobe signal is based at least in part on the calibration mode (paragraph 0054; i.e., there may be a self-calibrating mode in which the data strobe signal is received to train the data strobe gating signals).
Regarding Claim 5, Best teaches wherein the calibration mode (paragraph 0018) comprises the host device determining the timing relationship between the data strobe signal and the internal clock signal (paragraph 0018).
Regarding Claim 6, Prakash discloses wherein the read mode follows the calibration mode (paragraph 0054; i.e., the data strobe gating signals would need to be trained before the host is capable of correctly sampling the data).
Regarding Claim 7, Prakash discloses wherein the data pin is one of a plurality of data pins of the memory device (Figure 1, items 18; i.e., there may be a plurality of data pins that connect the host 12 to the memory device 14).
Regarding Claim 8, Prakash discloses wherein the data pin is one of a set of data pins (DAT[N:0]), wherein N is a positive integer (Figure 1, items 18; i.e., there may be a plurality of data pins that connect the host 12 to the memory device 14).
Regarding Claim 9, Prakash discloses in the calibration mode, using the host device: providing a first control signal using a general-purpose input/output (GPIO) pin of the host device (Figure 1, item 20, paragraph 0052; i.e., the pin of the host device 12 that connects to the clock/command block 20 is interpreted as a GPIO pin).
providing a first read command (paragraph 0053) to the memory device configured to trigger the memory device to provide the data strobe signal on a data strobe pin of the memory device (paragraph 0053; i.e., the data strobe DQS can be received).
Regarding Claim 10, Prakash discloses in a data read mode, using the host device: providing a second control signal using the GPIO pin; providing a second read command to the memory device; and in response to the second read command, receiving the read data at the host device (paragraphs 0053-0054; i.e., the read data DQ can be received).
Regarding Claim 11, Best teaches in the data read mode, receiving the data strobe signal from the memory device without providing the data strobe signal to the host device (paragraphs 0017-0018 and 0048; i.e., the data strobe signal is intermittent [not always received at the host device]), wherein the memory device has a dedicated data strobe pin (Figure 6, item 208), and the host device does not include a dedicated data strobe pin (Prakash teaches this feature in Figure 1, item 22, where the single pin 22 receives both a data signal and data strobe signal).
Regarding Claim 12, Best teaches intermittently triggering the calibration mode to determine the timing relationship between the data strobe signal and the internal clock signal to control a delay value of a delay circuit (Figure 3, item 52) using the timing relationship (paragraphs 0017-0018 and 0048).
Claims 13-21 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash, Bains et al. (U.S. Patent Application Publication Number 2009/0132888), and Best.
Regarding Claims 13 and 19, Prakash discloses a system (Figure 1, item 10) (and a non-transitory, computer-readable medium having stored thereon instructions and a processor - it is implied that a computer-readable medium with a processing mechanism is present in order to execute the algorithm described in claim 19 of Prakash) comprising:
a memory device (Figure 1, item 14, paragraphs 0053-0054) configured to output signals to a data pin (Figure 1, item 22) of a host device (Figure 1, item 12), wherein the signals are used to receive a data signal (Figure 1, item DQ) and a data strobe signal (Figure 1, item DQS) at the data pin, and the data signal comprises read data stored in the memory device (paragraph 0054);
the host device configured to:
receive a first signal of the signals at the data pin of the host device at a first time (paragraph 0054; i.e., a data strobe DQS signal is received);
interpret the first signal as the data strobe signal based at least in part on a set first mode (paragraph 0054; i.e., the data strobe signal DQS is transmitted from the memory to the host 12 during a read mode);
receive a second signal of the signals at the data pin of the host device at a second time (paragraph 0054; i.e., the second signal is the data DQ signal, which may be received at a second time);
interpret the second signal as the data signal based at least in part on a set second mode (paragraph 0054; i.e., the single DQ/DQS line is used to receive both a DQ signal and DQS signal; the host device 12 determines when to interpret the received signal as data [DQ] or strobe [DQS]);
wherein the second set mode comprises a data read mode (paragraph 0054; i.e., the data signals and data strobe signals are both received in the data read mode).
Prakash does not expressly disclose wherein the signals are used to time multiplex a data signal and a data strobe signal;
determine a timing relationship between the data strobe signal at the data pin of the host device and an internal clock signal;
control sampling of the data signal at the data pin of the host device using the determined timing relationship between the data strobe signal in the second set mode without the data strobe signal being received in the second set mode.
In the same field of endeavor (e.g., data sampling techniques), Bains teaches wherein the signals are used to time multiplex a data signal (Figure 4, item “RD CRC”) and a data strobe signal (i.e., a TDQS signal) (paragraph 0030).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Bains’ teachings of data sampling techniques with the teachings of Prakash, for the purpose of ensuring that collision does not occur on the data line between the data signals and data strobe signals.
Also In the same field of endeavor (e.g., data sampling techniques), Best teaches determine a timing relationship (paragraph 0017) between the data strobe signal (Figure 3, item DQS) at the data pin of the host device (Figure 3, item 50, paragraph 0020; i.e., a memory controller) and an internal clock signal (Figure 3, item CLK and Figure 6, item 201, paragraph 0028);
control sampling (Figure 3, item DSS) of the data signal at the data pin of the host device using the determined timing relationship between the data strobe signal in the second set mode without the data strobe signal being received in the second set mode (paragraphs 0017-0018 and 0048; i.e., the adjusted internal clock signal CLK is used instead of the data strobe signal DQS; the data strobe signal is intermittent [not always simultaneously received at the host device]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Best’s teachings of data sampling techniques with the teachings of Prakash, for the purpose of reducing sampling errors and providing a better sampling reference between the host and memory (see Best, paragraphs 0006 and 0023).
Regarding Claim 14, Prakash discloses wherein the set first mode comprises a read mode, and interpreting the received second signal as the data signal is based at least in part on the read mode (paragraphs 0053-0054; i.e., read data is sent from the memory device to the host in a read mode).
Regarding Claim 15, Prakash discloses wherein the set second mode comprises a calibration mode, and interpreting the received first signal as a data strobe signal is based at least in part on the calibration mode (paragraph 0054; i.e., there may be a self-calibrating mode in which the data strobe signal is received to train the data strobe gating signals).
Regarding Claim 16, Best teaches wherein the calibration mode (paragraph 0018) comprises the host device determining the timing relationship between the data strobe signal and the internal clock signal (paragraph 0018).
Regarding Claim 17, Prakash discloses wherein the read mode follows the calibration mode (paragraph 0054; i.e., the data strobe gating signals would need to be trained before the host is capable of correctly sampling the data).
Regarding Claim 18, Best teaches a delay circuit (Figure 3, item 52) configured to adjust a delay based at least in part on the determined timing relationship (paragraphs 0017-0018).
Regarding Claim 20, Prakash discloses wherein the second set mode comprises a calibration mode where the first signal is interpreted as the data strobe signal (paragraph 0054; i.e., there may be a self-calibrating mode in which the data strobe signal is received to train the data strobe gating signals), wherein the data read mode follows the calibration mode (paragraph 0054; i.e., the data strobe gating signals would need to be trained before the host is capable of correctly sampling the data).
Regarding Claim 21, Best teaches wherein the instructions are configured to cause the processor to adjust a programmable delay based at least in part on the determined timing relationship between the data strobe signal and the internal clock signal (paragraph 0017-0018).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses methods for providing data and strobe signals to a host device.
Response to Arguments
Applicant’s arguments with respect to claim 2 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached on Monday - Friday, 8 am - 5 pm, alternate Fridays.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175