DETAILED ACTION
This action is responsive to the following communication: the response filed 2/3/2026. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-3, 5, 7-10, 12, 14-16, 18 pending.
Claim Objections
The claim(s) is/are objected to because of the following informalities:
Claim 8: it appears that “a programming workload” in line(s) 14 was meant to be -- the programming workload --.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function.
Such claim limitation(s) is/are: “control means” in claim(s) 1-2, 5, and 7.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 9, and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 2, 9, and 15 recites “to acquire a smart verify programming voltage” in line 12. It is unclear whether this limitation is different from “acquire a smart verify program voltage” in respective claims 1, 8, and 14 to which the limitation depends. For purposes of examination, the limitation is considered the same, and will be construed as such. Therefore, it appears that “to acquire a smart verify programming voltage” in line 12 of claims 2, 9, and 15 was meant to be --to acquire the smart verify program voltage--.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishikawa et al. (US 2019/0096487 ‒hereinafter Nishikawa).
Regarding claim 7, Nishikawa discloses a memory apparatus, comprising:
memory cells (MT0-MT7; fig. 4) grouped into a plurality of blocks (BLK0-BLK3; fig. 1); and
a control means (200; fig. 1) configured to:
begin programming (fig. 6) a set of the memory cells (i.e. any set of memory cells among MT0-MT7) in a programming workload (receive from controller 200 instruction to write data, i.e. programming workload; fig. 7A), and
skip acquiring (“programming for parameter tuning” is skipped in which “programming with tuned parameter” is performed through order S32, S38, S39, S40, S34; fig. 6, 8) a smart verify program voltage (detected program voltage as optimal program voltage is not acquired when “programming for parameter tuning” is skipped; para 0124) used while programming the set of the memory cells (program run progress corresponding to “programming with tuned parameter”; fig. 6) in response to determining (S32; fig. 8) ones of the memory cells of the set (MT0-MT7) being disposed in one of the plurality of blocks (BLK) different than others of the memory cells being programmed during the programming workload (i.e. considered in different blocks since write destination block has been changed; fig. 8, Yes S32), and
wherein the set of the memory cells is selected (i.e. selected “programming with tuned parameter”) to prevent worse programming performance (i.e. to prevent more time spend on performing the programming; para 0124) than if no smart verify operation is used at all (i.e. than programming without smart verify operation; fig. 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8-10, 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishikawa et al. (US 2019/0096487 ‒hereinafter Nishikawa).
Regarding claim 1, Nishikawa discloses a memory apparatus, comprising:
memory cells (MT0-MT7; fig. 4) grouped into a plurality of blocks (BLK0-BLK3; fig. 1), within each block (within each block BLK; fig. 4), the memory cells being connected to a plurality of word lines (WL0-WL7; fig. 4) and disposed in memory holes (“a plurality of memory holes having lower ends reaching the p-well area 20 through the interconnect layers 25, 23, and 27” para 0108) and being organized in rows (i.e. rows of word lines; fig. 4) and grouped in a plurality of strings (10; fig. 4); and
a control means (200; fig. 1) configured to:
receive a programming workload (receive from controller 200 instruction to write data, i.e. programming workload; fig. 7A),
determine if a next two (i.e. a next and subsequent operations(s)) word line and string combinations (combinations of any word lines WL0-WL7 coupled to a string 10 in the next and subsequent write operations; para 0120) in the programming workload are in the same block (“determines whether the current write destination block address [i.e. to program the combinations] is the same as the last write destination block address” para 0128) of the plurality of blocks,
in response to determining (Yes S4; fig. 7B) that the next two word line and string combinations in the programming workload are in the same block (i.e. considered in the same block since the current and last write destination block addresses are the same; fig. 7B) of the plurality of blocks, acquire (S7; fig. 7B) a smart verify program voltage (a program voltage detected based on a smart verify reference voltage is acquired; fig. 6) in a smart verify operation (i.e. “programming for parameter tuning” fig. 6),
in response to determining (No S4; fig. 7B) that the next two word line and string combinations in the programming workload are not in the same block (i.e. considered not in the same block since the current and last write destination block addresses are not the same; fig. 7B), and
begin programming the memory cells (program run progress; fig. 6) according to the programming workload (fig. 6, 7A-7B).
Nishikawa does not expressly disclose [not in the same block], skip the smart verify operation.
Nishikawa, in an embodiment, teaches not in the same block (Yes S32, i.e. considered not in the same block since write destination block has been changed; fig. 8), skip the smart verify operation (the “programming for parameter tuning” is skipped in which “programming with tuned parameter” is performed through order S32, S38, S39, S40, S34; fig. 6, 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Nishikawa is modifiable as taught for the purpose of improving performance speeds in a highly integrated device (para 0145 of Nishikawa), which is common and well known in the art to reduce latencies to facilitate data accessing schemes and avoid points of failure that could otherwise hinder a complex system.
Regarding claim 2, Nishikawa discloses the memory apparatus, wherein during the smart verify operation, the control means is further configured to: perform at least one program-verify iteration of at least some of the memory cells (cell unit; para 0120) connected to a first word line and string combination (a first selected word line and string 10 combination; para 0120, 0123) using a voltage value (i.e. initial value; para 0123) which starts as a predetermined first initial voltage (Initial Vpgm; fig. 6) and is sequentially increased in each of a plurality of smart verify loops (i.e. corresponding to smart verify reference voltage; fig. 6) by a voltage step amount (ΔV; fig. 6) until a verify operation at a smart verify voltage (smart verify reference voltage; fig. 6) passes (i.e. is exceeded; para 0124) to acquire a smart verify programming voltage (detected program voltage as optimal program voltage; para 0124); and program (fig. 7A-7B) at least one of the memory cells in a second word line and string combination (i.e. memory cells of another word line coupled to a string 10 combination; para 0120, 0123) using the smart verify programming voltage acquired in the smart verify operation as a starting program voltage for programming (i.e. as an initial start program voltage in “programming with tuning parameter”; fig. 6).
Regarding claim 3, Nishikawa, in an embodiment, discloses the memory apparatus, wherein the first word line and string combination includes memory cells that are disposed in two of the plurality of strings (fig. 24).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Nishikawa is modifiable as taught for the purpose of improving performance speeds in a highly integrated device (para 0145 of Nishikawa), which is common and well known in the art to reduce latencies to facilitate data accessing schemes and avoid points of failure that could otherwise hinder a complex system.
Regarding claim 8, Nishikawa discloses a controller (200; fig. 1) in communication with a memory apparatus including memory cells (MT0-MT7; fig. 4) grouped into a plurality of blocks (BLK0-BLK3; fig. 1), within each block (within each block BLK; fig. 4), the memory cells being connected to a plurality of word lines (WL0-WL7; fig. 4) and disposed in memory holes (“a plurality of memory holes having lower ends reaching the p-well area 20 through the interconnect layers 25, 23, and 27” para 0108) and being organized in rows (i.e. rows of word lines; fig. 4) and grouped in a plurality of strings (10; fig. 4), the controller configured to:
receive a programming workload (receive from controller 200 instruction to write data, i.e. programming workload; fig. 7A);
determine if a next two (i.e. a next and subsequent operations(s)) word line and string combinations (combinations of any word lines WL0-WL7 coupled to a string 10 in the next and subsequent write operations; para 0120) in the programming workload are in the same block (“determines whether the current write destination block address [i.e. to program the combinations] is the same as the last write destination block address” para 0128) of the plurality of blocks,
in response to determining (Yes S4; fig. 7B) that the next two word line and string combinations in the programming workload are in the same block (i.e. considered in the same block since the current and last write destination block addresses are the same; fig. 7B) of the plurality of blocks, acquire (S7; fig. 7B) a smart verify program voltage (a program voltage detected based on a smart verify reference voltage is acquired; fig. 6) in a smart verify operation (i.e. “programming for parameter tuning” fig. 6),
in response to determining (No S4; fig. 7B) that the next two word line and string combinations in the programming workload are not in the same block (i.e. considered not in the same block since the current and last write destination block addresses are not the same; fig. 7B); and
instruct the memory apparatus to begin programming a set of the memory cells (program run progress; fig. 6) in a programming workload (fig. 6, 7A-7B).
Nishikawa does not expressly disclose [not in the same block], skip the smart verify operation.
Nishikawa, in an embodiment, teaches not in the same block (Yes S32, i.e. considered not in the same block since write destination block has been changed; fig. 8), skip the smart verify operation (the “programming for parameter tuning” is skipped in which “programming with tuned parameter” is performed through order S32, S38, S39, S40, S34; fig. 6, 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Nishikawa is modifiable as taught for the purpose of improving performance speeds in a highly integrated device (para 0145 of Nishikawa), which is common and well known in the art to reduce latencies to facilitate data accessing schemes and avoid points of failure that could otherwise hinder a complex system.
Regarding claim 9, Nishikawa discloses the controller, wherein during the smart verify operation, the controller is further configured to: instruct the memory apparatus to perform at least one program-verify iteration of at least some of the memory cells (cell unit; para 0120) connected to a first word line and string combination (a first selected word line and string 10 combination; para 0120, 0123) using a voltage value (i.e. initial value; para 0123) which starts as a predetermined first initial voltage (Initial Vpgm; fig. 6) and is sequentially increased in each of a plurality of smart verify loops (i.e. corresponding to smart verify reference voltage; fig. 6) by a voltage step amount (ΔV; fig. 6) until a verify operation at a smart verify voltage (smart verify reference voltage; fig. 6) passes (i.e. is exceeded; para 0124) to acquire a smart verify programming voltage (detected program voltage as optimal program voltage; para 0124); and instruct the memory apparatus to program (fig. 7A-7B) at least one of the memory cells in a second word line and string combination (i.e. memory cells of another word line coupled to a string 10 combination; para 0120, 0123) using the smart verify programming voltage acquired in the smart verify operation as a starting program voltage for programming (i.e. as an initial start program voltage in “programming with tuning parameter”; fig. 6).
Regarding claim 10, Nishikawa, in an embodiment, discloses the controller, wherein the first word line and string combination includes memory cells that are disposed in two of the plurality of strings (fig. 24).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Nishikawa is modifiable as taught for the purpose of improving performance speeds in a highly integrated device (para 0145 of Nishikawa), which is common and well known in the art to reduce latencies to facilitate data accessing schemes and avoid points of failure that could otherwise hinder a complex system.
Regarding claim 14, Nishikawa discloses a method of operating a memory apparatus including memory cells (MT0-MT7; fig. 4) grouped into a plurality of blocks (BLK0-BLK3; fig. 1), in each block (within each block BLK; fig. 4), the memory cells being connected to a plurality of word lines (WL0-WL7; fig. 4) and disposed in memory holes (“a plurality of memory holes having lower ends reaching the p-well area 20 through the interconnect layers 25, 23, and 27” para 0108) and being organized in rows (i.e. rows of word lines; fig. 4) and grouped in a plurality of strings (10; fig. 4), the method comprising the steps of:
receiving a programming workload (receive from controller 200 instruction to write data, i.e. programming workload; fig. 7A),
determining if a next two (i.e. a next and subsequent operations(s)) word line and string combinations (combinations of any word lines WL0-WL7 coupled to a string 10 in the next and subsequent write operations; para 0120) in the programming workload are in the same block (“determines whether the current write destination block address [i.e. to program the combinations] is the same as the last write destination block address” para 0128) of the plurality of blocks,
in response to determining (Yes S4; fig. 7B) that the next two word line and string combinations in the programming workload are in the same block (i.e. considered in the same block since the current and last write destination block addresses are the same; fig. 7B) of the plurality of blocks, acquiring (S7; fig. 7B) a smart verify program voltage (a program voltage detected based on a smart verify reference voltage is acquired; fig. 6) in a smart verify operation (i.e. “programming for parameter tuning” fig. 6),
in response to determining (No S4; fig. 7B) that the next two word line and string combinations in the programming workload are not in the same block (i.e. considered not in the same block since the current and last write destination block addresses are not the same; fig. 7B), and
begining programming the memory cells (program run progress; fig. 6) according to the programming workload (fig. 6, 7A-7B).
Nishikawa does not expressly disclose [not in the same block], skipping the smart verify operation.
Nishikawa, in an embodiment, teaches not in the same block (Yes S32, i.e. considered not in the same block since write destination block has been changed; fig. 8), skipping the smart verify operation (the “programming for parameter tuning” is skipped in which “programming with tuned parameter” is performed through order S32, S38, S39, S40, S34; fig. 6, 8).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Nishikawa is modifiable as taught for the purpose of improving performance speeds in a highly integrated device (para 0145 of Nishikawa), which is common and well known in the art to reduce latencies to facilitate data accessing schemes and avoid points of failure that could otherwise hinder a complex system.
Regarding claim 15, Nishikawa discloses the method, wherein during the smart verify operation, the method further includes the steps of: performing at least one program-verify iteration of at least some of the memory cells (cell unit; para 0120) connected to a first word line and string combination (a first selected word line and string 10 combination; para 0120, 0123) using a voltage value (i.e. initial value; para 0123) which starts as a predetermined first initial voltage (Initial Vpgm; fig. 6) and is sequentially increased in each of a plurality of smart verify loops (i.e. corresponding to smart verify reference voltage; fig. 6) by a voltage step amount (ΔV; fig. 6) until a verify operation at a smart verify voltage (smart verify reference voltage; fig. 6) passes (i.e. is exceeded; para 0124) to acquire a smart verify programming voltage (detected program voltage as optimal program voltage; para 0124); and programming (fig. 7A-7B) at least one of the memory cells in a second word line and string combination (i.e. memory cells of another word line coupled to a string 10 combination; para 0120, 0123) using the smart verify programming voltage acquired in the smart verify operation as a starting program voltage for programming (i.e. as an initial start program voltage in “programming with tuning parameter”; fig. 6).
Regarding claim 16, Nishikawa, in an embodiment, discloses the method, wherein the first word line and string combination includes memory cells that are disposed in two of the plurality of strings (fig. 24).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Nishikawa is modifiable as taught for the purpose of improving performance speeds in a highly integrated device (para 0145 of Nishikawa), which is common and well known in the art to reduce latencies to facilitate data accessing schemes and avoid points of failure that could otherwise hinder a complex system.
Allowable Subject Matter
Claim(s) 5, 12, 18 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to the dependent claims 5, 12, and 18, the prior art fails to teach or suggest the claimed limitations, namely in response to determining that the next two word line and string combinations are in the same block, set a smart verify parameter to be enabled ;in response to determining that the next two word line and string combinations are not in the same block, set the smart verify parameter to be disabled ; and after programming the memory cells of the second word line and string combination, returning to determining whether the next two word line and string combinations are in the same block.
The allowable claims are supported in at least fig. 12-14 of the instant application.
Response to Arguments
Applicant’s arguments, filed , with respect to the rejection(s) under 35 USC § 102 and 35 USC § 103 have been fully considered and the previous non-final action has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the prior art(s) referenced in this subsequent non-final rejection.
Conclusion
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[AltContent: arrow] Primary Examiner, Art Unit 2824