DETAILED ACTION
This action is responsive to the following communication: the response filed 7/2/26. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-3, 5, 7-10, 12, 14-16, 18 pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishikawa et al. (US 2019/0096487 ‒hereinafter Nishikawa).
The disclosure of fig(s). 1-8 of Nishikawa is incorporated into an embodiment as considered below, since elements are analogous and similarly referenced (para 0288). Therefore, before the effective filing date of the invention, it would have been obvious to one with ordinary skill in the art to modify the figure(s) with the embodiment as taught for the purpose of improving performance speeds in a highly integrated device (para 0145 of Nishikawa), which is common and well known in the art to reduce latencies to facilitate data accessing schemes and avoid points of failure that could otherwise hinder a complex system.
Regarding claim 7, Nishikawa discloses a memory apparatus, comprising:
memory cells (MT0-MT7; fig. 4) grouped into a plurality of blocks (BLK0-BLK3; fig. 1); and
a control means (200; fig. 1) configured to:
begin programming (fig. 6) a set of the memory cells (i.e. any set of memory cells among MT0-MT7) in a programming workload (receive from controller 200 instruction to write data, i.e. programming workload; fig. 7A), and
set a smart verify enable parameter (a BL prefix command to select a register for smarty verify; para 0131+) to be disabled (the BL prefix is considered disabled when not attached in the programming workload, and/or when smart verify is not executed; para 0133) in response to determining (fig. 7C, 8) ones of the memory cells of the set being disposed in one of the plurality of blocks (BLK) different than others of the memory cells being programmed during the programming workload (i.e. considered in different blocks between one of a host, garbage collection, or another write destination block; fig. 7C, 8), and
skip acquiring (“programming for parameter tuning” is skipped in which “programming with tuned parameter” is performed through order S32, S38, S39, S40, S34; fig. 6, 8) a smart verify program voltage (detected program voltage as optimal program voltage is not acquired when “programming for parameter tuning” is skipped; para 0124) used while programming the set of the memory cells (program run progress corresponding to “programming with tuned parameter”; fig. 6) in response to the smart verify enable parameter being disable (fig. 7C, 8; further, smart verify may not be executed in which acquiring the smart verify program voltage is not performed, i.e. skipped; para 0133), and
wherein the set of the memory cells is selected (i.e. selected “programming with tuned parameter”) to prevent worse programming performance (i.e. to prevent more time spend on performing the programming; para 0124) than if no smart verify operation is used at all (i.e. than programming without smart verify operation; fig. 6).
Allowable Subject Matter
Claim(s) 1-3, 5, 8-10, 12, 14-16, 18 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior art made of record and not relied upon is considered pertinent to applicant’s disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to independent claim 1 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely in response to determining that the next two word line and string combinations are in the same block, set a smart verify enable parameter to be enabled, and after programming the memory cells of the second word line and string combination, returning to determining whether the next two word line and string combinations are in the same block.
With respect to independent claim 8 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely in response to determining that the next two word line and string combinations in the programming workload are in the same block, set a smart verify enable parameter to be enabled; in response to determining that the next two word line and string combinations in the programming workload are not in the same block, set the smart verify enable parameter to be disabled; and after programming the memory cells of the second word line and string combination, returning to the determining whether the next two word line and string combinations are in the same block.
With respect to independent claim 14 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely in response to determining that the next two word line and string combinations in the programming workload are in the same block of the plurality of blocks, setting a smart verify enable parameter to be enabled; in response to determining that the next two word line and string combinations in the programming workload are not in the same block of the plurality of blocks, setting the smart verify enable parameter to be disabled; and after programming the memory cells of the second word line and string combination, returning to determining whether the next two word line and string combinations are in the same block.
The allowable claims are supported in at least fig. 12-14 of the instant application.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 7/2/26 have been fully considered but are not persuasive.
The applicant submits that Nishikawa fails to disclose a specific enabling/disabling parameter (on page 10-11 of the response, regarding the pending claim(s)).
The examiner respectfully disagrees with the arguments. Nishikawa, in an embodiment, teaches that a smart verify operating may not be executed if disabled (“a command to disable the smart verify may be attached and the smart verify may not be executed, in step S20” para 0133), in response to determining that a write destination block is not in a particular block (fig. 7C, 8). Further, a BL prefix command is a specific parameter used to facilitate the smart verify (i.e. a smart verify enable parameter as required by the claim), that is considered to be disabled if not attached in a programming instruction (fig. 7C). Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Therefore, it is reasonable to interpret that in both the aforementioned, whether the smart verify operation is not executed and/or the parameter is not attached, the smart verify enable parameter is considered disabled.
For at least the aforementioned reasons, the rejection is deemed proper and made final.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to UYEN SMET whose telephone number is (571) 272-2267. The examiner can normally be reached M-F, 9 AM-5 PM.
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/UYEN SMET/
Primary Examiner, Art Unit 2824______
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