DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakano(USPGPUB DOCUMENT: 2012/0306079, hereinafter Nakano) in view of Okura (USPGPUB DOCUMENT: 2021/0028085, hereinafter Okura).
Re claim 1 Nakano discloses a semiconductor device comprising: a semiconductor substrate(12); a first metallic layer(42) provided over the semiconductor substrate(12); and a protective film(40/44) including an opening(since there is a break or juncture at 42a this may be interpreted as an opening), wherein the protective film(40/44) is made of a resin material[0080],wherein the first metallic layer(42) provided across a region that includes the opening in plan view,
Nakano does not discloses a second metallic layer provided on the first metallic layer(42); the protective film(40/44) being provided on the second metallic layer, wherein the protective film(40/44) is in contact with the second metallic layer, , wherein the first metallic layer(42) and the second metallic layer are each provided across a region that includes the opening in plan view, and wherein the second metallic layer has a part interposed between the first metallic layer(42) and the protective film(40/44).
Okura discloses in Fig 4 a second metallic layer(22/24 of Okura); the protective film(23/26 of Okura) being provided on the second metallic layer,
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Okura to the teachings of Nakano in order to suppress an occurrence of crack in a first metal layer [0004, Okura]. In doing so, a second metallic layer(22/24 of Okura) provided on the first metallic layer(42); the protective film(23/26 of Okura) being provided on the second metallic layer(22/24 of Okura), wherein the protective film(23/26 of Okura) is in contact with the second metallic layer(22/24 of Okura), , wherein the first metallic layer(42) and the second metallic layer(22/24 of Okura) are each provided across a region that includes the opening in plan view, and wherein the second metallic layer(22/24 of Okura) has a part interposed between the first metallic layer(42) and the protective film(40/44).
Re claim 2 Nakano and Okura disclose the semiconductor device according to claim 1, wherein, in plan view, at least a part of an outer edge of the second metallic layer(22/24 of Okura) coincides with an outer edge of the first metallic layer(42).
Re claim 3 Nakano and Okura disclose the semiconductor device according to claim 1, wherein, the second metallic layer(22/24 of Okura) includes a through hole that overlaps with the protective film(40/44) in plan view.
Re claim 4 Nakano and Okura disclose the semiconductor device according to claim 1, wherein the second metallic layer(22/24 of Okura) is made of Ni, an alloy of Ni, or Au.
Re claim 5 Nakano and Okura disclose the semiconductor device according to claim 4, wherein the second metallic layer(22/24 of Okura) has a thickness that is within a range of 1 micrometer or more and 5 micrometers or less.
Re claim 6 Nakano and Okura disclose the semiconductor device according to claim 4, further comprising a third metallic layer provided on the second metallic layer(22/24 of Okura), the third metallic layer(22/24 of Okura) being disposed in the opening in plan view, wherein the third metallic layer(22/24 of Okura) is made of Ni, an alloy of Ni, or Au.
Re claim 7 Nakano and Okura disclose the semiconductor device according to claim 6, wherein the second metallic layer(22/24 of Okura) has a thickness that is within a range of 1 micrometer or more and 2 micrometers or less.
Re claim 8 Nakano and Okura disclose the semiconductor device according to claim 6, wherein the third metallic layer(22/24 of Okura) has a thickness that is within a range of 1 micrometer or more and 3 micrometers or less.
Re claim 9 Nakano and Okura disclose the semiconductor device according to claim 4, wherein the first metallic layer(42) is made of Al or an alloy of Al.
Re claim 10 Nakano discloses a method for producing a semiconductor device, the semiconductor device including: a semiconductor substrate(12); a first metallic layer(42) provided over the semiconductor substrate(12); and a protective film(40/44) including an opening(since there is a break or juncture at 42a this may be interpreted as an opening), the method comprising: forming the first metallic layer(42) and forming the protective film(40/44), wherein the protective film(40/44) is made of a resin material[0080],wherein the first metallic layer(42) are each provided across a region that includes the opening in plan view,
Nakano does not discloses a second metallic layer provided on the first metallic layer(42); the protective film(40/44) being provided on the second metallic layer, the method comprising: the second metallic layer; wherein the protective film(40/44) is in contact with the second metallic layer, , wherein the second metallic layer are each provided across a region that includes the opening in plan view, and wherein the second metallic layer has a part interposed between the first metallic layer(42) and the protective film(40/44).
Okura discloses in Fig 4 a second metallic layer(22/24 of Okura); the protective film(23/26 of Okura) being provided on the second metallic layer,
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Okura to the teachings of Nakano in order to suppress an occurrence of crack in a first metal layer [0004, Okura]. In doing so, a second metallic layer(22/24 of Okura) provided on the first metallic layer(42); the protective film(23/26 of Okura) being provided on the second metallic layer(22/24 of Okura), the method comprising: the second metallic layer(22/24 of Okura); wherein the protective film(40/44) is in contact with the second metallic layer(22/24 of Okura), , wherein the second metallic layer(22/24 of Okura) are each provided across a region that includes the opening in plan view(since there is a break or juncture at 42a this may be interpreted as an opening), and wherein the second metallic layer(22/24 of Okura) has a part interposed between the first metallic layer(42) and the protective film(40/44).
Re claim 11 Nakano and Okura disclose the method according to claim 10, wherein the forming of the first metallic layer(42) and the second metallic layer(22/24 of Okura) includes: depositing a first metallic film over the semiconductor substrate(12); depositing a second metallic film on the first metallic film; and collectively etching the first metallic film and the second metallic film to form the first metallic layer(42) and the second metallic layer(22/24 of Okura).
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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