DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species A represented as figures 1-2, claims 1-3, 6-8, 10, 12-18, and 20 in the reply filed on July 22, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 26, 2024 was considered by the examiner.
Drawing Objections
The drawings are objected to because:
In ¶ 0019, Applicant states “bit plug DP” is shown in figure 2-6. There is no such element in figure 2. This is also the case in ¶ 0026.
Figure 1 needs to show element DP.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-8, 10, 12-18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Lee et al. (US 2024/0074173 A1) (“Lee”).
Regarding claim 1, Lee teaches at least in figures 2A and 5E:
a circuit structure (1st-CH);
a stack structure (2nd-CH) bonded onto the circuit structure (1st-CH) and including (equivalent to comprising; detailed below)
a plurality of molding layers (113) alternately stacked with a plurality of electrodes (111);
a source line (CSL and 115; hereinafter “CSL”) disposed on the stack structure (2nd-CH);
a channel structure (VHS) extending into the source line (CSL) through the stack structure (2nd-CH); and
an isolation insulating pattern (120) disposed in a slit (MC) that extends through the source line (CSL) and the stack structure (2nd-CH);
wherein the isolation insulating pattern (120) includes a first section adjacent (area around CSL; hereinafter “A”) to the source line (CSL) and a second section (area around 2nd-CH not including CSL; hereinafter “B”) adjacent to the stack structure (2nd-CH);
wherein the isolation insulating (120) pattern includes a convergence interface between the first section and the second section (detailed below); and
wherein the convergence interface (described below; hereinafter “C”) is disposed between an end of the channel structure (end of CHS) disposed in the source line (CSL) and a surface of the plurality of horizontal electrodes closest to the source line (111 closest to CSL) (Examiner note: the convergence interface can be any interface as all it requires is the limitation directly above).
Regarding claim 2, Lee teaches at least in figures 2A and 5E:
wherein a surface of the isolation insulating pattern (120) and a surface of the source line (CSL) are formed in substantially the same plane (120 and CSL share a plurality of same planes).
Regarding claim 3, Lee teaches at least in figures 2A and 5E:
wherein the convergence interface (C) is disposed between the end of the channel structure (VHS) and a first molding layer (113) of the plurality of molding layers (113),
wherein the first molding layer (113) is closer to the source line (CSL) than any of the plurality of molding layers (the other 113s).
Regarding claim 6, Lee teaches at least in figures 2A and 5E:
wherein the first section of the isolation insulating pattern has an inverted trapezoid shape, and wherein the second section of the isolation insulating pattern has a trapezoid shape (based upon Applicant’s figures 1 and 2 element 120 has the same shape).
Regarding claim 7, Lee teaches at least in figures 2A and 5E:
further comprising (detailed below):
a first insulating bonding layer disposed on the circuit structure; a first bonding pad in the first insulating bonding layer; a second insulating bonding layer disposed between the first insulating bonding layer and the stack structure and bonded to the first insulating bonding layer; and a second bonding pad disposed in the second insulating bonding layer and bonded to the first bonding pad (in figure 2A one can see there are at least two layers to HB, and in each layer there is a horizontal portion of a via. This feature meets the claim limitations above).
Regarding claim 8, Lee teaches at least in figures 2A and 5E:
further comprising (detailed below): an interlayer insulating layer between the first insulating bonding layer and the stack structure (a portion of 150 below VHS; hereinafter “D”); and
an interconnection (110) disposed in the interlayer insulating layer (D) and connected to the channel structure (VHS).
Regarding claim 10, Lee teaches at least in figures 2A and 5E:
wherein the channel structure (VHS) comprises (detailed below):
a channel pattern (CL) connected to the source line (CSL); and
a bit plug (not labeled in figure 2A, however, this is the box which connects 110 to CL; hereinafter “E”) contacting the channel pattern (CL),
wherein the interconnection (110) contacts the bit plug (E) at a first level (it so connects).
Regarding claim 12, Lee teaches at least in figures 2A and 5E:
wherein the channel structure (VHS) further comprises (detailed below)
a core layer (CL) that extends into the source line (CSL) through the stack structure (2nd-CH),
wherein the channel pattern (CL) surrounds a side surface and an end of the core layer (BIL), and
wherein the channel pattern (CL) directly contacts the source line (CSL as shown in figure 5N).
Regarding claim 13, Lee teaches at least in figures 2A and 5E:
wherein the channel structure (VHS) further comprises (detailed below)
an information storage pattern (DSL) between the channel pattern (CL) and the stack structure (2nd-CH), and
wherein an end of the information storage pattern (DSL) contacts the source line (CSL).
Regarding claim 14, Lee teaches at least in figures 2A and 5E:
wherein the information storage pattern (DSL) comprises (detailed below):
a tunnel layer on the channel pattern; a charge trap layer on the tunnel layer; and a blocking layer on the charge trap layer; wherein the charge trap layer is disposed between the tunnel layer and the blocking layer (¶ 0042).
Regarding claim 15, Lee teaches at least in figures 2A and 5E:
Claim 15 is broader than claim 1, and is rejected for the same reasons as claim 1 above.
Regarding claim 16, Lee teaches at least in figures 2A and 5E:
wherein the plurality of electrodes comprise: at least one source select line closest to the source line; at least one drain select line closest to a bit plug; and a plurality of word lines between the at least one source select line and the at least one drain select line (According to Applicant’s ¶ 0025, anyone of 155/165/175, the plurality of electrodes, can accomplish the above functions. There is nothing special about 155/165/175 other than the intended use of said electrodes. The prior art teaches the same structure with regards to element 111. Therefore, the prior art teaches the same structure as Applicant, and since they are the same structure one can use them for the same functions).
Regarding claim 17, Lee teaches at least in figures 2A and 5E:
Claim 17 is rejected for the same reasons as claim 8 above.
Regarding claim 18, Lee teaches at least in figures 2A and 5E:
Claim 18 is rejected for the same reasons as claim 10 and 13 above.
Regarding claim 20, Lee teaches at least in figures 2A and 5E:
Claim 20 is rejected for the same reasons as claim 14 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST.
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/VINCENT WALL/ Primary Examiner, Art Unit 2898
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