CTNF 18/647,764 CTNF 95812 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 4/26/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-14 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kinoshita (US 20080296056 A1) . Regarding claim 1, Kinoshita discloses a circuit board (Fig. 16) comprising: a substrate (a collection of structures, cited below in turn) including a first insulating layer (31; [0061]: “insulation layer”) with a first surface ( See annotated figure for surface designation) , and a cavity ([0110]: “cavity”, See annotated figure) penetrating (fully penetrating) the first insulating layer in a direction (vertical direction, See annotated figure for direction designation) perpendicular to the first surface; a first wiring layer (25) embedded in the first insulating layer and having at least one surface exposed from the first insulating layer (exposed at 48, enhanced clarity shown in Figs. 12-13) ; and a buffer portion (a portion of 31, See annotated figure) disposed adjacent (horizontally adjacent) to an edge of the cavity (45/46) in the first insulating layer and having a receiving surface ( See annotated figure for surface designation) retreated further from the at least one surface of the first wiring layer exposed from the first insulating layer (the surface is vertically retreated below the exposed surface of 25, enhanced clarity shown in Figs. 12-13) . Illustrated below is a marked and annotated figure of Fig. 16 of Kinoshita. PNG media_image1.png 308 575 media_image1.png Greyscale Regarding claim 2, Kinoshita discloses the circuit board of claim 1, wherein: the first wiring layer comprises a plurality of wiring patterns (27/28) , and the receiving surface of the buffer portion is retreated further (vertically further, enhanced clarity shown in Figs. 12-13) from the at least one surface of the first wiring layer exposed from the first insulating layer of an innermost wiring pattern (27) closest to the cavity (horizontally closest) among the plurality of wiring patterns. Regarding claim 3, Kinoshita discloses the circuit board of claim 2 (Fig. 16) , wherein: a first side surface of the innermost wiring pattern is covered (at least partially covered, enhanced clarity shown in Figs. 12-13) by the first insulating layer, and a second side surface of the innermost wiring pattern includes a portion exposed (at least partially exposed, enhanced clarity shown in Figs. 12-13) from the first insulating layer. Regarding claim 4, Kinoshita discloses the circuit board of claim 2 (Fig. 16) , wherein: the innermost wiring pattern comprises a portion of a side surface (27 vertically protrudes from 31, as shown with enhanced clarity Figs. 12-13, thus the vertical protrusion includes “a portion of a side surface” ) , exposed (directly exposed) toward the cavity. Regarding claim 5, Kinoshita discloses the circuit board of claim 1 (Fig. 16) , wherein: the at least one surface of the first wiring layer exposed from the first insulating layer is retreated further (vertically further) from the first surface of the first insulating layer. Regarding claim 6, Kinoshita discloses the circuit board of claim 1 (Fig. 16) , wherein: the receiving surface of the buffer portion is configured to face a same direction as the first surface of the first insulating layer ( See annotated figure showing these surfaces facing the same vertical direction) . Regarding independent claim 7, Kinoshita discloses an electronic device package (Fig. 16) comprising: a substrate (a collection of structures, cited below in turn) including a first insulating layer (31; [0061]: “insulation layer”) with a first surface ( See annotated figure for surface designation) , and a cavity ([0110]: “cavity”, See annotated figure) penetrating (fully penetrating) the first insulating layer in a direction (vertical direction, See annotated figure for direction designation) perpendicular to the first surface; a first wiring layer (25) embedded in the first insulating layer and having at least one surface exposed from the first insulating layer (exposed at 48, enhanced clarity shown in Figs. 12-13) ; a buffer portion (a portion of 31, See annotated figure) disposed adjacent (horizontally adjacent) to an edge of the cavity (45/46) in the first insulating layer and having a receiving surface ( See annotated figure for surface designation) retreated further from the at least one surface of the first wiring layer exposed from the first insulating layer (the surface is vertically retreated below the exposed surface of 25, enhanced clarity shown in Figs. 12-13) ; an electronic device (70; [0084]: “electronic components”) accommodated in the cavity; an insulation material (80; [0095]: “insulating resin”) disposed on (directly “on” ) the buffer portion to fill (completely “fill” ) a gap ( See annotated figure) between the electronic device and the first wiring layer and insulate the electronic device from the first wiring layer (as cited above, the material is an insulating resin, thus it insulates between these components) ; and a redistribution layer (16/38/39/40/41) disposed on (indirectly on) the first surface of the first insulating layer and to which the electronic device is connected (connected at least by 18) . Regarding claim 8, Kinoshita discloses the electronic device package of claim 7 (Fig. 16) , further comprising an insulation protective layer (2) disposed between (vertically between) the first surface of the first insulating layer and the redistribution layer to cover (indirectly “cover” ) the first wiring layer. Regarding claim 9, Kinoshita discloses the electronic device package of claim 7 (Fig. 16) , wherein: the first wiring layer comprises a plurality of wiring patterns (27/28) , and the receiving surface of the buffer portion is retreated further (vertically further, enhanced clarity shown in Figs. 12-13) from a first surface of an innermost wiring pattern (27) closest to the cavity (horizontally closest) among the plurality of wiring patterns exposed from the first insulating layer (27 is exposed from 31 to the cavity) . Regarding claim 10, Kinoshita discloses the electronic device package of claim 9 (Fig. 16) , wherein: a first side surface of the innermost wiring pattern is covered (at least partially covered, enhanced clarity shown in Figs. 12-13) by the first insulating layer, and a second side surface of the innermost wiring pattern includes a portion exposed (at least partially exposed, enhanced clarity shown in Figs. 12-13) from the first insulating layer. Regarding claim 11, Kinoshita discloses the electronic device package of claim 10 (Fig. 16) , wherein: the insulation material is disposed in contact (direct “contact” ) with the first side surface (a portion of the surface, the protruding portion shown with enhanced clarity in Figs. 12-13) of the innermost wiring pattern on the buffer portion. Regarding claim 12, Kinoshita discloses the electronic device package of claim 9 (Fig. 16) , wherein: the insulation material comprises a first surface ( See annotated figure for surface designation) disposed on (directly “on” ) the receiving surface of the buffer portion to be retreated further from the first surface of the innermost wiring pattern exposed from the first insulating layer. Regarding claim 13, Kinoshita discloses the electronic device package of claim 7 (Fig. 16) , wherein: the exposed first surface of the first wiring layer is retreated further (vertically further) from the first surface of the first insulating layer. Regarding claim 14, Kinoshita discloses the electronic device package of claim 7 (Fig. 16) , wherein: the receiving surface of the buffer portion is configured to face a direction that is same as the first surface of the first insulating layer ( See annotated figure showing these surfaces facing the same vertical direction) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks. 07-22-aia AIA Claim s 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kinoshita as applied to claim 7 above, and further in view of Ko (US 20200312801 A1) . Regarding claim 15, Kinoshita discloses the electronic package of claim 7 (Fig. 16) , however fails to teach the claimed material composition of the insulation material “wherein: the insulation material comprises a silicon oxide (SiO 2 ) filler” because Kinoshita only teaches a generic material composition for this insulation material ([0096]: “insulating resin”) . Ko discloses an insulation material in the same field of endeavor (Fig. 10: material 130) , wherein: the insulation material comprises a silicon oxide (SiO 2 ) filler ([0075]: “a resin including a reinforcing material such as an inorganic filler, for example, silica”) . Modifying the insulation material composition of Kinoshita (generic) by selecting from the finite selection of known suitable materials disclosed by Ko (specific) would arrive at the claimed insulation material. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the insulation material is performing the same function filling a cavity (Kinoshita: Fig. 16: material 80 filling the annotated cavity; Ko: Fig. 10: material 130 filling cavity 110H) . Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different material composition for the insulation material. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E). Illustrated below is Fig. 10 of Ko. PNG media_image2.png 447 508 media_image2.png Greyscale Regarding claim 16, Kinoshita discloses the electronic package of claim 7 (Fig. 16) , however fails to teach the claimed material composition of the insulation material “wherein: the insulation material comprises an Ajinomoto build-up film (ABF)” because Kinoshita only teaches a generic material composition for this insulation material ([0096]: “insulating resin”) . Ko discloses an insulation material in the same field of endeavor (Fig. 10: material 130) , wherein: the insulation material comprises an Ajinomoto build-up film (ABF) ([0075]: “ABF”) . Modifying the insulation material composition of Kinoshita (generic) by selecting from the finite selection of known suitable materials disclosed by Ko (specific) would arrive at the claimed insulation material. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the insulation material is performing the same function filling a cavity (Kinoshita: Fig. 16: material 80 filling the annotated cavity; Ko: Fig. 10: material 130 filling cavity 110H) . Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different material composition for the insulation material. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM H ANDERSON/ Examiner, Art Unit 2817 Application/Control Number: 18/647,764 Page 2 Art Unit: 2817 Application/Control Number: 18/647,764 Page 3 Art Unit: 2817 Application/Control Number: 18/647,764 Page 4 Art Unit: 2817 Application/Control Number: 18/647,764 Page 5 Art Unit: 2817 Application/Control Number: 18/647,764 Page 6 Art Unit: 2817 Application/Control Number: 18/647,764 Page 7 Art Unit: 2817 Application/Control Number: 18/647,764 Page 8 Art Unit: 2817 Application/Control Number: 18/647,764 Page 9 Art Unit: 2817 Application/Control Number: 18/647,764 Page 10 Art Unit: 2817
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