Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-14 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Byun (US 20210183774 A1).
Regarding claim 1, Byun discloses a circuit board (Fig. 7) comprising:
a substrate (110) including a first insulating layer (111c) with a first surface (See annotated figure), and a cavity (110H) extending through (completely “through”) the first insulating layer in a direction (vertical direction, See annotated figure for direction designation) perpendicular to the first surface;
a first wiring layer (113c/112d) embedded (partially “embedded”) in the first insulating layer and having at least one surface (See annotated figure) exposed from the first insulating layer, the first wiring layer being spaced apart from the cavity when viewed in the direction perpendicular to the first surface (wiring layer 113c/112d is fully outside the cavity 110H, thus it is “spaced apart” within the breadth of the claim, MPEP 2111); and
a buffer portion (encircled, See annotated figure) disposed adjacent (horizontally “adjacent”) to an edge of the cavity in the first insulating layer and having a receiving surface (See annotated figure) retreated further (vertically “retreated” lower, See annotated figure for direction designation) from the at least one surface of the first wiring layer exposed from the first insulating layer.
Illustrated below is a marked and annotated figure of Fig. 7 of Byun.
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Regarding claim 2, Byun discloses the circuit board of claim 1 (Fig. 7), wherein:
the first wiring layer comprises a plurality of wiring patterns (multiple 113c/112d are illustrated), and
the receiving surface of the buffer portion is retreated further (vertically “retreated”) from the at least one surface of the first wiring layer exposed from the first insulating layer of an innermost wiring pattern closest (horizontally “closest”) to the cavity among the plurality of wiring patterns.
Regarding claim 3, Byun discloses the circuit board of claim 2 (Fig. 7), wherein: a first side surface of the innermost wiring pattern (See annotated figure) is covered (horizontally “covered”) by the first insulating layer, and a second side surface of the innermost wiring pattern (One Surface, See annotated figure) includes a portion exposed (horizontally “exposed”) from the first insulating layer.
Regarding claim 4, Byun discloses the circuit board of claim 2 (Fig. 7), wherein: the innermost wiring pattern comprises a portion of a side surface (One Surface, See annotated figure), exposed (horizontally “exposed”) toward the cavity.
Regarding claim 5, Byun discloses the circuit board of claim 1 (Fig. 7), wherein: the at least one surface of the first wiring layer exposed from the first insulating layer is retreated further (vertically higher, See annotated figure for direction designation) from the first surface of the first insulating layer.
Regarding claim 6, Byun discloses the circuit board of claim 1 (Fig. 7), wherein: the receiving surface of the buffer portion is configured to face a same direction (vertical direction. Note, this surface is inclined so it at least partially faces “a same direction”) as the first surface of the first insulating layer.
Regarding independent claim 7, Byun discloses an electronic device package (Fig. 7) comprising:
a substrate (110) including a first insulating layer (111c) with a first surface (See annotated figure), and a cavity (110H) extending through (completely “through”) the first insulating layer in a direction (vertical direction, See annotated figure for direction designation) perpendicular to the first surface;
a first wiring layer (113c/112d) embedded (partially “embedded”) in the first insulating layer and having at least one surface (See annotated figure) exposed from the first insulating layer, the first wiring layer being spaced apart from the cavity when viewed in the direction perpendicular to the first surface (wiring layer 113c/112d is fully outside the cavity 110H, thus it is “spaced apart” within the breadth of the claim, MPEP 2111);
a buffer portion (encircled, See annotated figure) disposed adjacent (horizontally “adjacent”) to an edge of the cavity in the first insulating layer and having a receiving surface retreated further (vertically “retreated” lower, See annotated figure for direction designation) from the at least one surface of the first wiring layer exposed from the first insulating layer;
an electronic device (120) accommodated in the cavity;
an insulation material (130 within 110H) disposed on the buffer portion to fill a gap between (horizontally “between”) the electronic device and the first wiring layer and insulate the electronic device from the first wiring layer ([0059]: “it has insulating properties”); and
a redistribution layer (142/143) disposed on (vertically “on”) the first surface of the first insulating layer and to which the electronic device is connected (direct electrical connection is illustrated).
Regarding claim 8, Byun discloses the electronic device package of claim 7 (Fig. 7), further comprising an insulation protective layer (130 outside of 110H; [0059]: “it has insulating properties”) disposed between (vertically “between”) the first surface of the first insulating layer and the redistribution layer to cover (vertically “cover”) the first wiring layer.
Regarding claim 9, Byun discloses the electronic device package of claim 7 (Fig. 7), wherein:
the first wiring layer comprises a plurality of wiring patterns (multiple 113c/112d are illustrated), and
the receiving surface of the buffer portion is retreated further (vertically “retreated”) from a first surface (higher vertical surface, See annotated figure for direction designation) of an innermost wiring pattern closest t (horizontally “closest”) to the cavity among the plurality of wiring patterns exposed from the first insulating layer.
Regarding claim 10, Byun discloses the electronic device package of claim 9 (Fig. 7), wherein: a first side surface of the innermost wiring pattern (See annotated figure) is covered (horizontally “covered”) by the first insulating layer, and a second side surface of the innermost wiring pattern (One Surface, See annotated figure) includes a portion exposed (horizontally “exposed”) from the first insulating layer.
Regarding claim 11, Byun discloses the electronic device package of claim 10 (Fig. 7), wherein: the insulation material is disposed in contact (direct “contact”) with the second side surface of the innermost wiring pattern on the buffer portion.
Regarding claim 12, Byun discloses the electronic device package of claim 9 (Fig. 7), wherein: the insulation material comprises a first surface (See annotated figure for surface designation) disposed on (directly “on”) the receiving surface of the buffer portion to be retreated further from the first surface of the innermost wiring pattern exposed from the first insulating layer.
Regarding claim 13, Byun discloses the electronic device package of claim 7 (Fig. 7), wherein: the exposed first surface of the first wiring layer is retreated further (vertically higher, See annotated figure for direction designation) from the first surface of the first insulating layer.
Regarding claim 14, Byun discloses the electronic device package of claim 7, wherein: the receiving surface of the buffer portion is configured to face a direction that is same (vertical direction. Note, this surface is inclined so it at least partially faces “a direction that is same”) as the first surface of the first insulating layer.
Regarding claim 16, Byun discloses the electronic device package of claim 7 (Fig. 7), wherein: the insulation material comprises an Ajinomoto build-up film (ABF) ([0059]: “Ajinomoto Build-up Film (ABF)”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Byun as applied to claim 7 above, and further in view of Ko (US 20200312801 A1).
Regarding claim 15, Byun discloses the electronic device package of claim 7, wherein: the insulation material comprises a silicon oxide (SiO2) filler (Note: a generic inorganic filler is relied upon here. See additional remarks below regarding the material composition of this filler.).
Byun fails to teach specific material composition for the filler, beyond a generic inorganic composition ([0059]: “together with an inorganic filler”). Thus, Byun fails to teach “the insulation material comprises a silicon oxide (SiO2) filler”.
Ko discloses an insulation material in the same field of endeavor (Fig. 10: material 130), wherein: the insulation material comprises a silicon oxide (SiO2) filler ([0075]: “a resin including a reinforcing material such as an inorganic filler, for example, silica”). Modifying the filler material composition (of Byun: a generic inorganic filler) by selecting from the finite selection of known suitable materials disclosed by Ko (a specific inorganic filler) would arrive at the claimed filler material. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the filler is performing the same function filling a cavity (Byun: Fig. 7: material 130 filling the cavity 110H; Ko: Fig. 10: material 130 filling the cavity 110H). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different material composition for the filler. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E).
Illustrated below is Fig. 10 of Ko.
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Response to Arguments
Applicant's arguments filed 9/3/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claims 1 and 7 that Kinoshita “fails to disclose that “the first wiring layer is spaced apart from the cavity when viewed in the direction perpendicular to the first surface”, as recited in amended claims 1 and 7”. Remarks at pg. 6.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1 and 7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The amendments change the scope of the claims, thus necessitating the new ground of rejection in the instant Office action.
Applicant argues:
Applicant argues with respect to amended claim 11 that “Consistent with the asymmetry feature, Applicant has amended claim 11 to recite that “the insulation material is disposed in contact with the second side surface of the innermost wiring pattern on the buffer portion.””. Remarks at pg. 7.
Examiner’s reply:
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “asymmetric”) are not recited in the rejected claim(s). The examiner finds Applicant’s amendment and remarks supported and directed to the contended “asymmetric” features of the disclosure. However, the claim as written reasonably includes configurations beyond the specifically contended “asymmetric” configuration (MPEP 2111: Broadest Reasonable Interpretation). Accordingly, the claim is rejected in the instant Office action based on at least one reasonable alternative interpretation. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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