DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 18 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim 18 recites the broad recitation “at least 5 nm”, and the claim also recites “more specifically at least 15 nm”, which is the narrower statement of the range/limitation. The claim(s) are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 1-5, 7, 11, 15, 21, and 22 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Bersano, et al. “Quantum Dots Array on Ultra-Thin SOI Nanowires with Ferromagnetic Cobalt Barrier Gates for Enhanced Spin Qubit Control” in 2023 Symposium on VLSI Technology and Circuits, Digest of Technical Papers 2023 (listed in IDS filed 04/26/2024; “Bersano” hereafter).
Allowable Subject Matter
Claims 6, 8-10, 12-14, and 16-20, for claim 18 pending overcoming the rejection under 35 USC 112(b) (supra), are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 6, 8, 12, 15, 16, and 19 read,
6. The qubit device according to claim 1, wherein the confinement arrangement comprises two elongate confinement gates arranged side by side and a semiconductor element extending at least in the direction of the elongate confinement gates, and wherein the quantum dots are configured to be defined in the semiconductor element.
8. The qubit device according to claim 1, wherein the qubit device further comprises a respective adhesion layer placed between a respective control gate and the second dielectric for holding the respective control gate on the second dielectric and/or for forming a diffusion barrier between the respective control gate and the second dielectric.
12. The qubit device according to claim 1, wherein the control gates in the set of first types of control gates comprise a first control gate having a first width followed by at least two second control gates having a second, different width, wherein the width is measured along the longitudinal direction.
15. The qubit device according to claim 1, wherein the second types of control gates have mutually substantially the same width measured along the longitudinal direction.
16. The qubit device according to claim 1, wherein the second types of control gates form a first gate layer with a first distance to the confinement arrangement, and the first types of control gates form a second, different gate layer with a second, different distance to the confinement arrangement, the distance being measured orthogonally to the longitudinal direction.
19. The qubit device according to claim 1, wherein the qubit device further comprises a first inversion gate extending from a first end of the qubit device to a quantum dot region in a center region of the qubit device, and a second inversion gate extending from a second, opposite end of the qubit device to the quantum dot region, the first and second inversion gates extending longitudinally along the confinement arrangement and separated from the confinement arrangement by the second dielectric to thereby extend a respective electrically conductive doped region at a respective end of the qubit device to the quantum dot region.
The prior art does not reasonably teach or suggest—in the context of each of claims 6, 8, 12, 15, 16, and 19—the limitations recited therein.
Claims 9 and 10 would be allowable at least for including the same allowable limitations by depending from claim 8, either directly or indirectly.
Claims 13 and 14 would be allowable at least for including the same allowable limitations by depending from claim 12.
Claims 17 and 18 would be allowable at least for including the same allowable limitations by depending from claim 16.
Claim 20 would be allowable at least for including the same allowable limitations by depending from claim 19.
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 12,342,733 (“Lampert”) is cited for disclosing a qubit device including a plurality of control gates 130/136 made out of at least some ferromagnetic metal 130. With regard to claim 1, Lampert discloses, generally in Fig. 3I,
1. A qubit device 100 comprising:
[1] a semiconductor substrate [bulk silicon handle of the SOI substrate 102 (col. 10, lines 39-47)];
[2] an elongate confinement arrangement 146 [i.e. “quantum well stack 146” (col. 7, lines 1-47; Fig. 3I)] defining a longitudinal direction (i.e. at least the horizontal direction of the 2-D array shown in Figs 1 and 4-6];
[3] a first dielectric [i.e. the BOX of the SOI substrate] placed between the semiconductor substrate [bulk silicon handle of the SOI substrate] and the confinement arrangement 146 to electrically separate the confinement arrangement from the semiconductor substrate;
[4] a second dielectric [gate dielectric 140 (paragraph bridging cols. 13-14)] longitudinally at least partially electrically insulating the confinement arrangement;
[5a] a set of control gates [130/136 in “gate openings 103” Figs. 1, 3I] arranged longitudinally along the confinement arrangement and separated from the confinement arrangement by the second dielectric 140,
[5b] the set of control gates 130/136 being configured to define one or more quantum dots in the confinement arrangement,
[5c] a respective quantum dot being suitable for holding a spin qubit [col. 9, lines 6-21],
[5d] the set of control gates 130/136 comprising a set of first types of control gates [e.g. plunger gates] and a set of second, different types of control gates [e.g. barrier gates] …
[5e] wherein the first types of control gates are ferromagnetic gates 130/136 [col. 12, lines 1-25; col. 13, lines 14-37].
With regard to features [5b] and [5d] of claim 1, Lampert discloses plunger gates and barrier gates:
In some applications, some of the quantum dot gates of the quantum dot device 100 may be used as plunger gates to enable the formation of quantum dots under these gates, while some other ones of the quantum dot gates may be used as barrier gates to adjust the potential barrier between quantum dots formed under adjacent plunger gates.
(Lampert: col. 8, lines 23-29; emphasis added)
With regard to feature [5e] of claim 1, while all of the gates 130/136 include both ferromagnetic 130 and non-magnetic 136 metals, claim 1 does not exclude the second type of control gate from being magnetic.
Finally, with regard to feature [5d] of claim 1, Lampert does not disclose that the plunger and barrier gates are “arranged alternatingly along the confinement arrangement” as required by claim 1, simply stating that some gates are plunger gates and some are barrier gates. It is not clear that one having ordinary skill in the art would arrange the plunger gates and barrier gates “alternatingly along the confinement arrangement”, as required by the claim, given the two-dimensional array layout of the control gates shown in Figs. 1 and 4-6 of Lampert.
US 2023/0420548 (“Aldeghi”) is cited for disclosing ferromagnetic plunger gates P arranged alternatingly with barrier gate B along a nanowire 205, as required by features [2] and [5a]-[5e] of claim 1 (Aldeghi: ¶¶ 7, 29, 44; Fig. 2). However, Aldeghi does not disclose a semiconductor substrate, or either of the first and second dielectrics.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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