DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 in the reply filed on 29 July 2026 is acknowledged. Claim 20 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Claims 1-19 are examined. The Restriction/Election Requirement is made final.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 3-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karda et al. (“Karda” US 2022/0278112).
Regarding claim 1, Karda discloses a semiconductor memory device (Figures 5A-6B) comprising:
a first metal-oxide semiconductor film (520 left side connected to BL1/BL2, see Figure 6A);
a second metal-oxide semiconductor film (520 right side connected to BL3/BL4, see Figure 6A) spaced apart from the first metal-oxide semiconductor film (see Figure 6A);
a first gate electrode (241/541F) intersecting the first metal-oxide semiconductor film and the second metal-oxide semiconductor film (see Figures 6A and 5A);
a first gate dielectric film (515A/515B/525A/525B/526 left side under BL1/BL2 in Figure 6A) interposed between the first metal-oxide semiconductor film (520 left) and the first gate electrode (241/541F, see Figure 6A and para. [0089]);
a charge storage film (202) in the first gate dielectric film (515A/515B), the charge storage film extending along at least a portion of the first metal-oxide semiconductor film (520 left) and connected to the second metal-oxide semiconductor film (520 right, see Figure 6A);
a second gate electrode (214/541B, see Figures 5A and 6A) spaced apart from the first gate electrode (214/541B) and intersecting the second metal-oxide semiconductor film (520 right, see Figure 6A); and
a second gate dielectric film (515A/515B/525A/525B left side under BL3/BL4 in Figure 6A) interposed between the second metal-oxide semiconductor film (520 right) and the second gate electrode (214/514B, see Figure 6A).
Regarding claim 3, Karda discloses wherein the first gate dielectric film (515A/515B/525A/525B/526 left) includes a first sub-dielectric film (525A contacting BL2) covering a lower surface of the first metal-oxide semiconductor film (520 left, when rotating Figure 6A 90 degrees clockwise, portion 525A covers a lower surface of the first semi film 520 left, or upper when rotated), a second sub-dielectric film (526 connected to BL1 and BL2) covering an upper surface of the first metal-oxide semiconductor film (520 left, or upper when Figure 6A is rotated, covers an upper surface of portion of 520 connected to BL2), and a third sub-dielectric film (515A contacting BL1) covering an upper surface of the second sub-dielectric film (526 connected to BL1, see Figure 6A rotated clockwise), and
the charge storage film (202) is interposed between the second sub-dielectric film (526 connected to BL1) and the third sub-dielectric film (515A contacting BL1, see Figure 6A).
Regarding claim 4, Karda further discloses a contact (503Y) penetrating through the third sub-dielectric film (515A contacting BL3) and the second gate dielectric film (515A/515B/525A/525B left, see Figure 6A), the contact connected to the charge storage film (202) and to the second metal-oxide semiconductor film (520 right, or lower when rotating Figure 6A, here, “connected to” can mean either physical or electrical connection or both, Figure 6A shows physical connection either directly or through intervening layers).
Regarding claim 5, Karda discloses wherein the second gate dielectric film (515A/515B/525A/525B/526 right in Figure 6A) includes a first sub-dielectric film (525A, far right in Figure 6A) covering a lower surface of the second metal-oxide semiconductor film (520, right, see Figure 6A rotated 90 degrees clockwise), and a second sub-dielectric film (515A/515B connected to BL3) covering a side surface and an upper surface of the second metal-oxide semiconductor film (520 right, or lower when Figure 6A is rotated).
Regarding claim 6, Karda further discloses a substrate (599);
a circuit element (297) on the substrate (599);
a lower insulating film on the substrate (599, see para. [0070], a dielectric layer may be between elements 599 and 297), the lower insulating film covering the circuit element (297); and
a first wiring structure (BL1-BL4) and a second wiring structure (891-894, see Figure 8A) sequentially stacked on the lower insulating film (stacked horizontally when Figure 6A/8A is rotated),
wherein the first metal-oxide semiconductor film (520, left), the second metal-oxide semiconductor film (520, right), the first gate electrode (241/541F), and the second gate electrode (241/541B) are each interposed between the first wiring structure and the second wiring structure (see Figures 5A, 6A, 8A).
Regarding claim 7, Karda discloses wherein the first wiring structure includes a first wiring pattern (BL1) and a second wiring pattern (BL2) spaced apart from each other (see Figure 8A), and
the first metal-oxide semiconductor film (520, left) is connected to the first wiring pattern and the second wiring pattern (BL1 and BL2, see Figure 8A).
Regarding claim 8, Karda discloses wherein the second wiring structure (891-894) includes a third wiring pattern (894) connected to the second metal-oxide semiconductor film (520, right, see Figure 8A, physically connected to each other through intervening layers).
Regarding claim 9, Karda further discloses a third wiring structure (510) stacked on the second wiring structure (891-894, see Figure 8A, stacked horizontally when Figure 6A/8A is rotated),
wherein the third wiring structure (510) includes a fourth wiring pattern (510, left in Figure 6A) connected to the first gate electrode (541F, see Figure 5A and 6A) and a fifth wiring pattern (510, right) connected to the second gate electrode (541B, see Figure 5A and 6A).
Regarding claim 10, Karda discloses wherein each of the first metal-oxide semiconductor film and the second metal-oxide semiconductor film includes indium gallium zinc oxide (IGZO) (see para. [0083]).
Regarding claim 11, Karda discloses wherein the charge storage film (202) includes at least one of polysilicon or silicon nitride (see para. [0077]).
Allowable Subject Matter
Claims 2 and 12-19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record does not fairly disclose or make obvious the claimed device as a whole. Specifically, the closest prior art, which has been made of record, fail to disclose by themselves or in combination the limitations of “a second gate electrode intersecting the second metal-oxide semiconductor film and not intersecting the first metal-oxide semiconductor film” of claim 12 in combination with the additionally claimed features, as are claimed by Applicant, as well as the similar limitation of claim 2. The closest prior art, Karda ‘112, and the cited prior art does not show that the second gate electrode (one of the word lines 241) does not intersect the second semiconductor film (202), and it is the Examiner’s position that a person having ordinary skill in the art would see no motivation to incorporate the feature into the teachings of Karda. Here, the Examiner is interpreting the non-intersecting limitation to mean that the first metal oxide semiconductor film and the second gate electrode do not overlap/intersect physically in the cross-sectional view, this feature is shown in at least Fig. 2 of the instant application.
Thus, the listed claims are determined to be novel and non-obvious. Claims 13-19 are allowable based on their dependence on claim 12.
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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