DETAILED ACTION
This Office Action is in response to Application filed April 26, 2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Species I drawn to the embodiment shown in Fig. 2 of current application, claims 1-3, in the reply filed on August 14, 2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claim 1, it is not clear what “a semiconductor laminated structure” recited on line 2 refers to, because (a) the term “a semiconductor laminated structure” per se can be broadly interpreted, (b) however, Applicants do not claim “a semiconductor laminated structure” per se, but further claim that “a ratio of a thickness of the semiconductor laminated structure with respect to the gate length is 4.0 or less” on lines 9-10, (c) the transitional phrase “including” recited on line 2 does not preclude presence of another layer or other layers included in the semiconductor laminated structure in addition to the claimed electron transit layer and the electron supplying layer recited on lines 2-3, and (d) therefore, the limitation “a ratio of a thickness of the semiconductor laminated structure with respect to the gate length is 4.0 or less” recited on lines 9-10 may or may not be met by a single semiconductor device depending on what “a semiconductor laminated structure” includes, and whether the semiconductor laminated structure consists of the electron transit layer and the electron supplying layer or the semiconductor structure includes the electron transit layer, the electron supplying layer and another layer or other layers such as (i) a p-GaN gate layer, (ii) an AlN insertion layer disposed between the electron transit layer and the electron supplying layer to improve density of a two-dimensional electron gas generated inside the electron transit layer, (iii) another or second electron supplying layer formed of AlGaN to improve density of a two-dimensional electron gas generated inside the electron transit layer, and so on.
(2) Further regarding claim 1, it is not clear what “a gate length” recited on line 8 refers to, because (a) the term “a gate length” per se can be broadly interpreted, (b) however, Applicants do not claim “a gate length” per se, but further claim that “a ratio of a thickness of the semiconductor laminated structure with respect to the gate length is 4.0 or less” on lines 9-10, (c) as shown in Fig. 2 of current application, the gate electrode has a T-shape, which has at least two gate lengths including the Lg and the largest length of the gate electrode measured at the top surface of the gate electrode, which is longer than the Lg shown in Fig. 2 of current application, and (d) therefore, the limitation “a ratio of a thickness of the semiconductor laminated structure with respect to the gate length is 4.0 or less” recited on lines 9-10 may or may not be met by a single semiconductor device depending on what “a gate length” refers to since (i) there are at least two gate lengths shown in Fig. 2 of current application, and (ii) therefore, there are at least two ratios “of a thickness of the semiconductor laminated structure with respect to the gate length” even if arguendo there is only one thickness of the semiconductor laminated structure.
Claims 2 and 3 depend on claim 1, and therefore, claims 2 and 3 are also indefinite.
(3) Regarding claim 3, it is not clear what the limitation “he buffer layer having an Al composition x which is 0.2 or higher” recited on lines 2-3 suggests, because (a) it is not clear what “an Al composition x” refers to since Applicants do not claim any formula including “Al” and “x”, and (b) therefore, it is not clear whether the buffer layer is formed of, for example, AlxN, AlxGa1-xN, AlxIn1-xN, AlxAs, GaN:Alx or GaN doped with Al, etc.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, as best understood, are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Inoue et al. (US 2009/0045438)
Regarding claims 1-3, Inoue et al. disclose a method for manufacturing a semiconductor device (Fig. 2) comprising: forming a semiconductor laminated structure (composite structure of 4 and 5), including an electron transit layer (4) and an electron supplying layer (5), above an AIN substrate (2 or composite structure of 1 and 2), because (a) Merriam-Webster dictionary defines “substrate” as “an underlying support”, and therefore, the AlN Nucleation Layer 2 can be referred to as a substrate since it supports the semiconductor layer stack deposited on it, and (b) in addition, “an AlN substrate” can be interpreted as a substrate comprising AlN, in which case the composite structure of the Substrate 1 and the AlN Nucleation Layer 2 can be referred to as “an AlN substrate” just like (i) a silicon-on-insulator (SOI) substrate can be referred to as a silicon substrate, and (ii) a silicon substrate covered with a native oxide can be referred to as a silicon substrate; forming a gate electrode (8), a source electrode (6), and a drain electrode (7) above the electron supply layer, wherein the electron transit layer is located at a lowermost position of the semiconductor laminated structure, the gate electrode has a gate length of 0.3 µm or less ([0059], [0062], [0302], [0323] and [0345]), and a ratio of a thickness of the semiconductor laminated structure (composite structure of 4 and 5) with respect to the gate length of the gate electrode is 4.0 or less ([0043]), because (a) Inoue et al. disclose that “an aspect ratio Lg/a of an active layer thickness a, which is defined as a total of a film thickness of the electron supply layer and a film thickness of the channel layer under the gate electrode, to a gate length Lg fulfills Lg/a≥5” in paragraph [0043] and in numerous other parts of the same patent publication of Inoue et al., (b) therefore, the claimed “ratio of a thickness of the semiconductor laminated structure with respect to the gate length of the gate electrode” would be expressed as “a/Lg” in Inoue et al., which would be ≤ 0.2 when “Lg/a≥5”, and (c) the ratio of “a/Lg” ≤ 0.2 is included in the claimed range of “4.0 or less” recited on lines 9-10 (claim 1), further comprising: forming a buffer layer (3) above the substrate (2 or composite structure of 1 and 2) before the forming the semiconductor laminated structure (composite structure of 4 and 5), wherein the forming the semiconductor laminated structure forms the semiconductor laminated structure on the buffer layer (claim 2), wherein the forming the buffer layer (3) forms the buffer layer having an Al composition x which is 0.2 or higher (Fig. 8), because (a) this limitation is indefinite as discussed above under 35 USC 112(b) rejections, and (b) Applicants do not claim whether the buffer layer has a uniform material composition (claim 3).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Inoue et al. (US 9,954,087)
Miyamoto et al. (US 7,863,648)
Tamai et al. (US 2009/0212324)
Nakata (US 10,790,385)
Endoh (US 9,000,488)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 August 28, 2026
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