Prosecution Insights
Last updated: July 17, 2026
Application No. 18/648,180

Integrated Assemblies and Methods of Forming Integrated Assemblies

Non-Final OA §102§103
Filed
Apr 26, 2024
Priority
Aug 20, 2020 — divisional of 12/015,080
Examiner
QUINTO, KEVIN V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
725 granted / 854 resolved
+16.9% vs TC avg
Minimal +2% lift
Without
With
+1.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
25 currently pending
Career history
884
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
76.3%
+36.3% vs TC avg
§102
13.6%
-26.4% vs TC avg
§112
5.1%
-34.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 854 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 9 and 18 are objected to because of the following informalities: the phrase, “being uniquely address,” is grammatically incorrect. Appropriate correction is required. For purposes of examination, the above phrase in claims 9 and 18 has been interpreted as being uniquely addressed. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 5, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ramaswamy et al. (United States Patent Application Publication No. US 2020/0111917 A1, hereinafter “Ramaswamy”). In reference to claim 1, Ramaswamy discloses a method which meets the claim. Fig. 2A-4B of Ramaswamy discloses a method of forming an integrated assembly which comprises forming conductive features (112, 204) over a semiconductor base (102, 202). The conductive features (112, 204) comprise a first conductive material (p. 2-3, paragraph 22). The conductive features (112, 204) are spaced from one another by intervening insulative regions (126). A construction comprises the conductive features (112, 204) and the insulative regions (126). An upper surface of the construction includes conductive portions (112, 204) corresponding to upper surfaces of the conductive features (112, 204) and includes insulative portions (126) corresponding to upper surfaces of the intervening insulative regions (126). A second conductive material (113, 213) is selectively formed over the conductive portions (112, 204) relative to the insulative portions (126). Access device pillars (114, 230) are formed over the second conductive material (113, 213). Ramaswamy discloses (p. 6, paragraph 53) that the access device pillars (114, 230) include channel material which comprises semiconductor material having at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table in the form of IGZO (indium gallium zinc oxide). Insulative material (122, 222) is formed along one or more sidewalls of each of the access device pillars (114, 230). Conductive gates (124’, 124”, 224) are formed adjacent the insulative material (113, 213). Ramaswamy discloses (p. 3, paragraph 24) that storage elements are formed over the access device pillars (114, 230) and gatedly coupled to the conductive features (112, 204) through the channel material of the access device pillars (114, 230). With regard to claim 2, Ramaswamy discloses (p. 6, paragraph 53) that the semiconductor material for the access device pillars (114, 230) is a semiconductor oxide in the form of IGZO (indium gallium zinc oxide). In reference to claim 5, the conductive features (112, 204) are first linearly-extending features which extend along a first direction: (112) in the X-direction and (204) in the Y-direction. With regard to claim 11, fig. 2A-4B of Ramaswamy discloses forming a second insulative material (126, 226) over the conductive gates (124’, 124”, 224) and between the access device pillars (114, 230). There is a second construction comprising the access device pillars (114, 230) and the second insulative material (126, 226). The second construction has an upper surface with second conductive portions (117) corresponding to upper surfaces of the access device pillars (114, 230) and with second insulative portions (126, 226) between the second conductive regions (117) and comprises the second insulative material (126, 226). A third conductive material (116) is selectively formed over the second conductive portions (117) relative to the second insulative portions (126, 226). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ramaswamy in view of Lee et al. (United States Patent Application Publication No. US 2016/0148858 A1, hereinafter "Lee"). In reference to claim 3, Ramaswamy does not disclose the exact deposition method, such as ALD (atomic layer deposition), for the second conductive material (113, 213 - fig. 2A-4B of Ramaswamy) as that claimed by the applicant. However Lee discloses that forming a conductive material by ALD results in a material having superb film quality (p. 7, paragraph 98). In view of Lee, it would therefore be obvious to form the second conductive material of Ramaswamy by ALD. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ramaswamy in view of Yamazaki et al. (United States Patent Application Publication No. US 2010/0051949 A1, hereinafter "Yamazaki"). In reference to claim 4, Ramaswamy discloses (p. 6, paragraph 53) that the access device pillars (114, 230 - fig. 2A-4B of Ramaswamy) include channel material which comprises semiconductor material in the form of IGZO (indium gallium zinc oxide). Ramaswamy discloses that the second conductive material (113 - fig. 3A-4B of Ramaswamy) acts as the source contact while an upper conductive contact (116 - fig. 2A-4B of Ramaswamy) acts as the drain contact (p. 3, paragraph 26). It is understood that the second conductive material (213) in fig. 2A-2H also acts as a source contact. Ramaswamy does not disclose that the access device pillars (114, 230 - fig. 2A-4B of Ramaswamy) comprise conductive oxide regions above and below the channel material/region. However Yamazaki discloses forming conductive oxide source and drain regions from IGZO by implementing it to be oxygen deficient (p. 1, paragraphs 17-19). Yamazaki discloses that this is done in order to attain a lower contact resistance (p. 1-2, paragraphs 20-21) which is a known goal in the art (p. 1, paragraphs 9 and 10). In view of Yamazaki, it would therefore be obvious to implement conductive oxide regions above and below the channel material/region in the method disclosed by Ramaswamy. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ramaswamy in view of Wu (United States Patent Application Publication No. US 2021/0265267 A1, hereinafter "Wu"). In reference to claim 6, fig. 2A-4B of Ramaswamy show that the second conductive material (113, 213) are formed over the first linearly-extending features (112, 204). Ramaswamy does not disclose that the second conductive material (113, 213 - fig. 2A-4B of Ramaswamy) are shaped like domed caps. However figure 1 of Wu discloses (p. 5-6, paragraph 73) the use of a domed shape cap (121a) over a conductive plug (119a'). Wu discloses that implementing a round top surface in a conductive structure provides an evenly distributed electric field in the structure which leads to an improved lifespan and reliability of the device (p. 4, paragraph 51). In view of Wu, it would therefore be obvious to form the second conductive material (113, 213 - fig. 2A-4B of Ramaswamy) over the first linearly-extending features (112, 204 - fig. 2A-4B of Ramaswamy) to have a domed cap shape. Claims 7, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Ramaswamy in view of Bronner et al. (USPN 6,767,789 B1, hereinafter "Bronner"). In reference to claim 7, fig. 2A-2H of Ramaswamy shows that the conductive gates (124’, 124”, 224) extend along a second direction: (124’, 124”) in the Y-direction and (224) in the X-direction. Fig. 3A-4b shows that the second direction (Y-direction) of the conductive gates (124’, 124”) cross the first direction (X-direction). Fig. 2F shows that the second direction (X-direction) of the conductive gates (224) cross the first direction (Y-direction). Ramaswamy discloses that the individual gates are part of single continuous word lines (p. 3, paragraph 28); this can also be seen in fig. 1A. Ramaswamy does not disclose that the conductive gates (124’, 124”, 224) are along second linearly-extending features which also extend along the second direction which crosses the first direction. However Bronner discloses that using separate gate conductors which are coupled to separate word lines is functionally equivalent to using a gate that is part of a continuous word line (column 10, lines 20-26). The examiner would like to point out MPEP § 2144.06: In order to rely on equivalence as a rationale supporting an obviousness rejection, the equivalency must be recognized in the prior art, and cannot be based on applicant’s disclosure or the mere fact that the components at issue are functional or mechanical equivalents. In re Ruff, 256 F.2d 590, 118 USPQ 340 (CCPA 1958). In view of the above and the functional equivalence disclosed by Bronner, it would therefore be obvious to implement second linearly-extending features in the form of word lines which extend along and are coupled to the conductive gates in the second direction which crosses the first direction in the method disclosed by Ramaswamy. In reference to claim 12, Ramaswamy discloses a similar method. Fig. 2A-4B of Ramaswamy discloses a method of forming an integrated assembly which comprises forming first linearly-extending conductive structures (112, 204) over a semiconductor base (102, 202). The first linearly-extending conductive structures (112, 204) extend along a first direction: (112) in the X-direction and (204) in the Y-direction. Access device pillars (114, 230) are formed over the first linearly-extending conductive structures (112, 204). Ramaswamy discloses (p. 6, paragraph 53) that the access device pillars (114, 230) include channel material which comprises semiconductor material having at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table in the form of IGZO (indium gallium zinc oxide). A first insulative material (122, 222) is formed along one or more sidewalls of each of the access device pillars (114, 230). Conductive gates (124’, 124”, 224) are formed adjacent the first insulative material (113, 213). Fig. 2A-2H of Ramaswamy shows that the conductive gates (124’, 124”, 224) extend along a second direction: (124’, 124”) in the Y-direction and (224) in the X-direction. Fig. 3A-4b shows that the second direction (Y-direction) of the conductive gates (124’, 124”) cross the first direction (X-direction). Fig. 2F shows that the second direction (X-direction) of the conductive gates (224) cross the first direction (Y-direction). Ramaswamy discloses that the individual gates are part of single continuous word lines (p. 3, paragraph 28); this can also be seen in fig. 1A. Ramaswamy does not disclose that the conductive gates (124’, 124”, 224) are along second linearly-extending features which also extend along the second direction which crosses the first direction. However Bronner discloses that using separate gate conductors which are coupled to separate word lines is functionally equivalent to using a gate that is part of a continuous word line (column 10, lines 20-26). The examiner would like to point out MPEP § 2144.06: In order to rely on equivalence as a rationale supporting an obviousness rejection, the equivalency must be recognized in the prior art, and cannot be based on applicant’s disclosure or the mere fact that the components at issue are functional or mechanical equivalents. In re Ruff, 256 F.2d 590, 118 USPQ 340 (CCPA 1958). In view of the above and the functional equivalence disclosed by Bronner, it would therefore be obvious to implement second linearly-extending features in the form of word lines which extend along and are coupled to the conductive gates in the second direction which crosses the first direction in the method disclosed by Ramaswamy. A second insulative material (126, 226) is formed over the conductive gates (124’, 124”, 224) and between the access device pillars (114, 230). There is a construction comprising the access device pillars (114, 230) and the second insulative material (126, 226). The construction has an upper surface with conductive regions (117) corresponding to upper surfaces of the access device pillars (114, 230) and with insulative portions (126, 226) between the conductive regions (117) and comprises the second insulative material (126, 226). A conductive capping material (116) is selectively formed over the conductive regions (117) relative to the insulative portions (126, 226). Ramaswamy discloses (p. 3, paragraph 24) that storage elements are formed over the access device pillars (114, 230); the storage elements are coupled with the conductive capping material (116). With regard to claim 13, Ramaswamy discloses (p. 6, paragraph 53) that the semiconductor material for the access device pillars (114, 230) is a semiconductor oxide in the form of IGZO (indium gallium zinc oxide). Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ramaswamy in view of Bronner as applied to claim 7 above and as further evidenced by Singh et al. (United States Patent Application Publication No. US 2003/0174535 A1, hereinafter "Singh"). In reference to claim 8, Ramaswamy discloses that the first linearly-extending features (112, 204 - fig. 2A-4B of Ramaswamy) are bit lines (p. 3, paragraph 23). In the method of Ramaswamy constructed in view of Bronner, the conductive gates (124’, 124”, 224 - fig. 2A-4B of Ramaswamy) are coupled to the word lines. Ramaswamy also makes it clear that access device pillars are a part of an array (p. 2, paragraphs 20-21). Ramaswamy does not explicitly disclose that the bit lines/first linearly-extending features (112, 204 - fig. 2A-4B of Ramaswamy) are electrically coupled with sensing circuitry or that the word lines/conductive gates (124’, 124”, 224 - fig. 2A-4B of Ramaswamy) are electrically coupled with driver circuitry. However Singh makes it clear that electrically coupling bit lines to sensing circuitry and electrically coupling word lines to driver circuitry is necessary for accessing/reading data in a memory array (p. 1, paragraphs 2-4). Therefore claim 8 is not patentable over the above cited references. With regard to claim 9, Ramaswamy makes it clear that access device pillars are a part of an array (p. 2, paragraphs 20-21). As noted above with regard to claim 8, it is understood that the bit lines/first linearly-extending features (112, 204 - fig. 2A-4B of Ramaswamy) are electrically coupled with sensing circuitry while the word lines/conductive gates (124’, 124”, 224 - fig. 2A-4B of Ramaswamy) are electrically coupled with driver circuitry for accessing/reading data in the memory array. The operation of reading data in a storage element in an individual memory cell is performed by using one of the bit lines/first linearly-extending features (112, 204 - fig. 2A-4B of Ramaswamy) and one of the word lines/conductive gates (124’, 124”, 224 - fig. 2A-4B of Ramaswamy) to uniquely address the corresponding access device pillar/transistor (114, 230 – fig. 2A-4B of Ramaswamy) that is connected to the desired storage element. Thus claim 9 is not patentable over the above cited references. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ramaswamy in view of Price (United States Patent Application Publication No. US 2007/0213954 A1, hereinafter "Price"). In reference to claim 10, Ramaswamy does not disclose that the insulative material (122, 222 - fig. 2A-4B of Ramaswamy) or gate oxide material comprises a high-k composition. However Price discloses that using a high-k composition material for the gate oxide allows for a smaller device size while maintaining a low leakage current density which is desirable in the art (p. 1, paragraph 5). In view of Price, it would therefore be obvious to use a high-k composition material for the insulative material/gate oxide (122, 222 - fig. 2A-4B of Ramaswamy) in the method disclosed by Ramaswamy. Claims 14 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ramaswamy in view of Bronner as applied to claim 12 above and further in view of Wu. In reference to claim 14, Ramaswamy does not disclose that the conductive capping material (116 - fig. 2A-4B of Ramaswamy) are shaped like domed caps. However figure 1 of Wu discloses (p. 5-6, paragraph 73) the use of a domed shape cap (121a) over a conductive plug (119a'). Wu discloses that implementing a round top surface in a conductive structure provides an evenly distributed electric field in the structure which leads to an improved lifespan and reliability of the device (p. 4, paragraph 51). In view of Wu, it would therefore be obvious to form the conductive capping material (116 - fig. 2A-4B of Ramaswamy) over the conductive regions (117 - fig. 2A-4B of Ramaswamy) to have a domed cap shape. In reference to claim 19, Ramaswamy does not disclose that the conductive capping material (116 - fig. 2A-4B of Ramaswamy) over the conductive regions (117 - fig. 2A-4B of Ramaswamy) are conductive caps shaped like domed caps. However figure 1 of Wu discloses (p. 5-6, paragraph 73) the use of a domed shape cap (121a) over a conductive plug (119a'). Wu discloses that implementing a round top surface in a conductive structure provides an evenly distributed electric field in the structure which leads to an improved lifespan and reliability of the device (p. 4, paragraph 51). In view of Wu, it would therefore be obvious to form the conductive capping material (116) over the conductive regions (117 - fig. 2A-4B of Ramaswamy) to have a domed cap shape. Ramaswamy discloses (p. 3, paragraph 24) that storage elements are formed over the access device pillars (114, 230 - fig. 2A-4B of Ramaswamy); it is understood that are conductive interconnects between the access device pillars (114, 230 - fig. 2A-4B of Ramaswamy) and the storage elements. Thus in the method of Ramaswamy constructed in view of Bronner and Wu, the storage elements are electrically coupled with the conductive caps (116 - fig. 2A-4B of Ramaswamy) by conductive interconnects formed over in contact with the conductive caps (116 - fig. 2A-4B of Ramaswamy). Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ramaswamy in view of Bronner as applied to claim 12 above and further in view of Lee. In reference to claim 15, Ramaswamy does not disclose the exact deposition method, such as ALD (atomic layer deposition), for the conductive capping material (116 - fig. 2A-4B of Ramaswamy) as that claimed by the applicant. However Lee discloses that forming a conductive material by ALD results in a material having superb film quality (p. 7, paragraph 98). In view of Lee, it would therefore be obvious to form the conductive capping material by ALD. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Ramaswamy in view of Bronner as applied to claim 12 above and further in view of Yamazaki. In reference to claim 16, Ramaswamy discloses (p. 6, paragraph 53) that the access device pillars (114, 230 - fig. 2A-4B of Ramaswamy) include channel material which comprises semiconductor material in the form of IGZO (indium gallium zinc oxide). Ramaswamy discloses a source contact (113 - fig. 3A-4B of Ramaswamy) while the conductive region (117 - fig. 2A-4B of Ramaswamy) acts as part of the drain contact (p. 3, paragraph 26). It is understood that the material (213) in fig. 2A-2H also acts as a source contact. Ramaswamy does not disclose that the access device pillars (114, 230 - fig. 2A-4B of Ramaswamy) comprise conductive oxide regions above and below the channel material/region. However Yamazaki discloses forming conductive oxide source and drain regions from IGZO by implementing it to be oxygen deficient (p. 1, paragraphs 17-19). Yamazaki discloses that this is done in order to attain a lower contact resistance (p. 1-2, paragraphs 20-21) which is a known goal in the art (p. 1, paragraphs 9 and 10). In view of Yamazaki, it would therefore be obvious to implement conductive oxide regions above and below the channel material/region in the method of Ramaswamy constructed in view of Bronner. Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ramaswamy in view of Bronner as applied to claim 12 above and as further evidenced by Singh. In reference to claim 17, Ramaswamy discloses that the first linearly-extending features (112, 204 - fig. 2A-4B of Ramaswamy) are bit lines (p. 3, paragraph 23). In the method of Ramaswamy constructed in view of Bronner, the conductive gates (124’, 124”, 224 - fig. 2A-4B of Ramaswamy) are coupled to the word lines. Ramaswamy also makes it clear that access device pillars are a part of an array (p. 2, paragraphs 20-21). Ramaswamy does not explicitly disclose that the bit lines/first linearly-extending features (112, 204 - fig. 2A-4B of Ramaswamy) are electrically coupled with sensing circuitry or that the word lines/conductive gates (124’, 124”, 224 - fig. 2A-4B of Ramaswamy) are electrically coupled with driver circuitry. However Singh makes it clear that electrically coupling bit lines to sensing circuitry and electrically coupling word lines to driver circuitry is necessary for accessing/reading data in a memory array (p. 1, paragraphs 2-4). Therefore claim 17 is not patentable over the above cited references. With regard to claim 18, Ramaswamy makes it clear that access device pillars are a part of an array (p. 2, paragraphs 20-21). As noted above with regard to claim 8, it is understood that the bit lines/first linearly-extending features (112, 204 - fig. 2A-4B of Ramaswamy) are electrically coupled with sensing circuitry while the word lines/conductive gates (124’, 124”, 224 - fig. 2A-4B of Ramaswamy) are electrically coupled with driver circuitry for accessing/reading data in the memory array. The operation of reading data in a storage element in an individual memory cell is performed by using one of the bit lines/first linearly-extending features (112, 204 - fig. 2A-4B of Ramaswamy) and one of the word lines/conductive gates (124’, 124”, 224 - fig. 2A-4B of Ramaswamy) to uniquely address the corresponding access device pillar/transistor (114, 230 – fig. 2A-4B of Ramaswamy) that is connected to the desired storage element. Thus claim 18 is not patentable over the above cited references. Claims 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Ramaswamy in view of Bronner and further in view of Wu as applied to claim 19 above and further in view of Hsieh (United States Patent Application Publication No. US 2011/0006362 A1, hereinafter “Hsieh”). In reference to claim 20, in the method of Ramaswamy constructed in view of Bronner and Wu, the storage elements are electrically coupled with the conductive caps (116 - fig. 2A-4B of Ramaswamy) by conductive interconnects formed over in contact with the conductive caps (116 - fig. 2A-4B of Ramaswamy). Ramaswamy does not disclose that the conductive interconnects comprise metal nitride configured as upwardly-opening container shapes with a metal-containing core material within the upwardly-opening container shapes. However fig. 5 of Hsieh discloses (p. 4, paragraph 32) a conductive interconnect which comprises metal nitride (150’) configured as upwardly-opening container shapes (150’) with a metal-containing core material (145’) within the upwardly-opening container shapes (150’). Hsieh discloses that such a structure provides a contact with a low resistance (p. 4, paragraph 30) which is a known goal in the art (p. 1, paragraph 7). In view of Hsieh, it would therefore be obvious to implement conductive interconnects that comprise metal nitride configured as upwardly-opening container shapes with a metal-containing core material within the upwardly-opening container shapes. With regard to claim 21, Hsieh discloses that the metal nitride (150’) comprises titanium nitride while the core (145’) comprises tungsten (p. 4, paragraph 32). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEVIN QUINTO/Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Apr 26, 2024
Application Filed
May 16, 2024
Response after Non-Final Action
Jul 02, 2026
Non-Final Rejection mailed — §102, §103 (current)

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