Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/22/2026 has been entered.
Remarks
The allowance dated 02/27/2026 was withdrawn by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-6 and 15-17, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over MAKALA (Pub. No.: US 2021/0327890) in view of Zhang (Pub. No.: US 2021/0225864)
Re claim 1, MAKALA teaches a method of forming a microelectronic device, the method comprising:
forming a slit opening (49 of FIG. 7A) extending through a stack structure and into a source structure underlying the stack structure, the stack structure comprising a vertically alternating sequence of insulative structures (32) and conductive structures (42);
forming a dielectric liner (52/53 of FIG. 7I) within the slit opening, the dielectric liner substantially covering surfaces of the stack structure and source structure (11/10) defining boundaries of the slit opening;
forming a semiconductive fill material (601/602) within the slit opening and on the dielectric liner (52/53), the semiconductive fill material electrically isolated from the source structure and the stack structure by the dielectric liner (52/53). the forming the semiconductive fill material within the slit opening and on the dielectric liner comprises forming a polysilicon fill material (601/602) within the slit opening and on the dielectric liner (52/53);
removing an upper portion of the semiconductive fill material (601/602, FIG. 7N → 6P) from an upper region of the slit opening comprises removing an upper portion of the polysilicon fill material (601/602, FIG. 7N → 7P) from the upper region of the slit opening;
forming a conductive structure within the upper portion of the slit opening remaining after removing the upper portion of the semiconductive fill material, the conductive structure completely vertically overlying the void (49’) and comprising side surfaces substantially surrounded by the dielectric liner; and
forming contact openings vertically extending to and exposing at least some of the conductive structures simultaneous to removing the upper portion of the polysilicon fill material.
In re claims 1, MAKALA differs from the invention by not showing a conductive as a metal material.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the above said teaching because metal is a very well-known material for making a contact since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416.
Furthermore, MAKALA fails to teach the semiconductive fill material defining a void in a lower region thereof; forming staircase contact openings vertically extending to and exposing at least some of the conductive structures at a staircase structure simultaneous to removing an upper portion of the semiconductive fill material; and forming contact openings vertically extending to and exposing at least some of the conductive structures simultaneous to removing the upper portion of the polysilicon fill material.
Zhang teaches the semiconductive fill material (320, FIG. 3H, [0064]) defining a void in a lower region thereof (the white space in the middle of 320); forming staircase contact openings (325/327 of FIG. 3E) vertically extending to and exposing at least some of the conductive structures (332 of FIG. 3D) at a staircase structure simultaneous to removing an upper portion of the semiconductive fill material (320); and forming contact openings (325 of FIG. 3E) vertically extending to and exposing at least some of the conductive structures (332 of FIG. 3D) simultaneous to removing the upper portion of the polysilicon fill material (320).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the flexibility of manufacturing the 3D memory device as taught by Zhang, [0003].
Re claim 4, in the combination, Zhang, FIG. 3F teaches the method of claim 1, further comprising forming conductive contacts (343/345) in the contact openings simultaneous to forming the metal structure (340).
Re claim 5, in the combination, Zhang, FIG. 3E teaches the method of claim 4, further comprising:
forming a hard mask (336) over the stack structure;
forming openings in the hard mask extending over the slit opening (324); and
forming additional openings (325) in the hard mask over a staircase structure.
Re claim 6, MAKALA teaches a method of forming a microelectronic device, the method comprising:
forming at least one slit opening (49 of FIG. 7A) extending through a stack structure comprising a vertically alternating sequence of insulative structures (32) and conductive structures (42);
forming a dielectric liner (52/53 of FIG. 7I) within the at least one slit opening;
forming a polysilicon fill material (601) adjacent to the dielectric liner within the at least one slit opening;
forming a hard mask (602) over the stack structure;
forming openings in the hard mask (opening formed above 602) extending over the at least one slit opening.
MAKALA fails to teach forming additional openings in the hard mask over a staircase structure; removing a portion of the polysilicon fill material within the at least one slit opening; forming staircase contact openings vertically extending to and exposing at least some of the conductive structures at the staircase structure simultaneous to removing a portion of the polysilicon fill material within the at least one slit opening; forming a metal structure within a portion of the at least one slit opening remaining after removing the portion of the polysilicon fill material, side surfaces and a bottom surface of the metal structure substantially surrounded by the dielectric liner; and forming conductive contacts in the staircase contact openings simultaneous to forming the metal structure.
Zhang teaches forming additional openings in the hard mask (336) over a staircase structure;
removing a portion of the polysilicon fill material (320) within the at least one slit opening; forming staircase contact openings vertically extending to and exposing at least some of the conductive structures at the staircase structure (332 of FIG. 3E) simultaneous to removing a portion of the polysilicon fill material (topmost surface of 320) within the at least one slit opening;
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forming a metal structure (340 of FIG. 3F) within a portion of the at least one slit opening remaining after removing the portion of the polysilicon fill material (320 of FIG. 3E), side surfaces and a bottom surface of the metal structure substantially surrounded by the dielectric liner ([DL]. FIG 3 H [as shown above]); and
forming conductive contacts (357/359) in the staircase contact openings simultaneous to forming the metal structure (354).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the flexibility of manufacturing the 3D memory device as taught by Zhang, [0003].
Re claim 15, MAKALA teaches a method of forming a microelectronic device, comprising:
forming a trench (49 of FIG. 5b) vertically extending completely through a stack structure (32/42) and into a source structure, ¶ [0086]) underlying the stack structure, the stack structure comprising tiers respectively including conductive material (42, [0069]) and insulative material (32) vertically neighboring the insulative material;
forming dielectric liner material (52/53 of FIG. 7I) on surfaces of the stack structure and the source structure defining boundaries of the trench;
forming semiconductor material (601/602 of FIG. 7L of FIG. 3E) on surfaces of the dielectric liner material within the trench, the dielectric liner material electrically isolating the semiconductor material from the stack structure and the source structure, the forming semiconductor material on surfaces of the dielectric liner material (52/53) within the trench comprises only partially filling a remaining portion of the trench (49’) with the semiconductor material (601/602);
removing an upper portion of the semiconductor material (601/602, FIG. 7N → 7P) within the trench comprises forming an additional trench vertically overlying the void space within the remaining portion of the trench, a portion of the remaining portion of the semiconductor material vertically interposed between the additional trench and the void space; and
forming conductive material (63) within the trench after removing the upper portion of the semiconductor material, the conductive material in physical contact with a remaining portion of the semiconductor material (601/602); the forming metal material within the trench (49’ of FIG. 7L) comprises substantially filling the additional trench with the conductive material (63) without substantially filling the void space with the conductive material.
In re claims 15, MAKALA differs from the invention by not showing a conductive as a metal material.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the above said teaching because metal is a very well-known material for making a contact since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416.
Furthermore, MAKALA fails to teach forming semiconductor material (320, FIG. 3H, [0064]) having inner side surfaces partially defining a void space (the white space in the middle of 320); and forming staircase contact openings vertically extending to and exposing at least some conductive structures at a staircase structure simultaneous to removing an upper portion of the semiconductive fill material;
Zhang teaches forming semiconductor material (320, FIG. 3H, [0064]) having inner side surfaces partially defining a void space (the white space in the middle of 320); and forming staircase contact openings (325 of FIG. 3E) vertically extending to and exposing at least some conductive structures (332 of FIG. 3D) at a staircase structure simultaneous to removing an upper portion of the semiconductive fill material (320);
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the flexibility of manufacturing the 3D memory device as taught by Zhang, [0003].
Re claim 16, in the combination, MAKALA teaches the method of claim 15, wherein:
forming semiconductor material on surfaces of the dielectric liner material (52/53) within the trench comprises only partially filling a remaining portion of the trench with the semiconductor material (601/602); and
removing an upper portion of the semiconductor material (FIG. 7L → 7N) comprises forming an additional trench vertically extending to the void space within the remaining portion of the trench.
Re claim 17, in the combination, Zhang teaches the method of claim 16, wherein forming metal material (340/342/345 of FIG. 3F) within the trench comprises substantially filling each of the additional trench and the void space (324/325/327 of FIG. 3E) with the metal material.
Re claim 20, in the combination, MAKALA teaches the method of claim 15, wherein forming a trench comprises horizontally recessing the conductive material (42 of FIG. 14A) of the tiers relative to the insulative material of the tiers (32 of FIG. 15).
Conclusion
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/TONY TRAN/Primary Examiner, Art Unit 2893
Prosecution Insights