Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 4/28/2024.
Claims 1-18 are currently pending.
Claims 1-18 have been examined.
Priority
Applicant' s claim for the benefit of prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to Chinese Patent Application No. 202321031878.2, filed on Apr. 28, 2023, and the priority of a Chinese Patent Application No. 202322292211.4, filed on Aug. 24, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: LED DISPLAY DEVICE ARRAY, LED DISPLAY DEVICE, AND DISPLAY PANEL WITH CONNECTING WIRE HAVING A LINEAR CONNECTING SEGMENT.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1-3, and 5-6 recites the limitation "the connecting segment" in the last element of claim 1. There is insufficient antecedent basis for this limitation in the claim. Applicant is advised to either amend the claim either “a connecting segment” clarifying this is different from the previously stated “linear connecting segment” or to change each instance of “the connecting segment” to “the linear connecting segment”.
Claims 3 and 7-11 are rejected based on their dependence to claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. US 20190259736 A1 (hereinafter Li.).
The following annotated figure from Li will be used in discussion.
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Regarding claim 1, Li discloses:
A light-emitting diode (LED) display device array (Li, Figs.3-8b, surface mounted RGB LED packaging module), comprising
a substrate, (Fig. 8a, substrate 1)
at least two display units disposed on an upper surface of the substrate, and ([0056], The packaging module has two light emitting units.)
at least two pin assemblies (annotated Fig. 8a, first pin assembly 31 and second pin assembly 32) disposed on a lower surface of the substrate and in one-to-one correspondence with the at least two display units, (See Fig. 8a.)
wherein a cutting line (Fig. 8b, cutting lines 7) is disposed on the substrate between any two adjacent pin assemblies; (See Fig. 8a)
each of the at least two pin assemblies comprises at least two pins, and the at least two pins comprise a first pin and a second pin; (annotated Fig. 8a, fist pin assembly 31 including first pin in the first pin assembly 311 and second pin in the first pin assembly 312 and second pin assembly 32 including first pin in the second pin assembly 321 and second pin in the second pin assembly 322.)
a first pin in one of the at least two pin assemblies is misaligned with a second pin in an adjacent one of the at least two pin assemblies, (second pin in the first pin assembly 312 is misaligned from first pin in the second pin assembly 321) and the first pin and the second pin are connected to each other through a connecting wire (electroplating circuits 6); and
the connecting wire (electroplating circuits 6) has a linear connecting segment (annotated Fig. 8a, circuit line segment 600), and the connecting segment of the connecting wire intersects with the cutting line and is perpendicular to the cutting line. (See annotated Fig. 8a.)
Regarding claim 2, Li further discloses:
a length of the connecting segment of the connecting wire is greater than a width of the cutting line. (See annotated Fig. 8a. The width of the circuit line segment 600 is wider than the cutting line 7.)
Regarding claim 3, Li further discloses:
the connecting wire (annotated Fig. 8a, electroplating circuits 6)further has a first pin connecting segment (first pin connecting segment 601) and a second pin connecting segment; (second pin connecting segment 602)
an end of the first pin connecting segment is connected to the first pin, and another end of the first pin connecting segment is connected to an end of the connecting segment; and (See annotated Fig. 8a.)
an end of the second pin connecting segment is connected to the second pin, and another end of the second pin connecting segment is connected to another end of the connecting segment. (See annotated Fig. 8a.)
Regarding claim 4, Li further discloses:
each of the first pin connecting segment and the second pin connecting segment is a straight line or a curve. (See annotated Fig. 8a, the first pin connecting segment 601 and second pin connecting segment are a straight line.)
Regarding claim 5, Li further discloses:
each of the first pin connecting segment (first pin connecting segment 601) and the second pin connecting segment( second pin connecting segment 602) is a straight line, (See Fig. 8a.) and the first pin connecting segment and the second pin connecting segment are perpendicular to the connecting segment. (See annotated Fig. 8a, the first pin connecting segment 601 and second pin connecting segment are a straight line and have a part of the connecting segment that is perpendicular electroplating circuit 6.)
Regarding claim 6, Li further discloses:
each of the first pin connecting segment and the second pin connecting segment is a straight line; and (See annotated Fig. 8a, the first pin connecting segment 601 and second pin connecting segment are a straight line.)
the first pin connecting segment is perpendicular to the connecting segment,( See annotated Fig. 8a, the first pin connecting segment 601 has a part of the connecting segment that is perpendicular electroplating circuit 6.) and the second pin connecting segment is collinear with the connecting segment, (See annotated Fig. 8a, second pin connecting segment are a straight line and have a part of the connecting segment that is collinear to electroplating circuit 6.) or the second pin connecting segment is perpendicular to the connecting segment, and the first pin connecting segment is collinear with the connecting segment.
Regarding claim 7, Li further discloses:
further comprising a cover plate; (Fig. 7, isolating frame)
wherein the cover plate covers the upper surface of the substrate; (Fig. 7, isolating frame 9 is on top of the substrate 1.)
the cover plate is provided with through holes, and the through holes form accommodation cavities with the substrate, (Fig. 5, metal holes 3 which are on the substrate.) the accommodation cavities are in one-to-one correspondence with the display units; and (Fig. 7, isolating frame 9 has areas which are considered through holes as it goes through the frame to open to the substrate and the display units are placed in that area.
the at least two display units comprises at least one pixel assembly (See Fig. 8a, each display unit includes a RGB LED chip 4), and each of the at least one pixel assembly is disposed in a respective accommodation cavity. ([0050], the RGB LED chip 4 is displaced on the upper pad 2 which is in the equivalent of the accommodation cavity.)
Regarding claim 10, Li further discloses:
at least one pad assembly is disposed on the upper surface of the substrate, (upper pad 2 is disposed on the substrate) the at least one pad assembly is in one-to-one correspondence with the at least one pixel assembly,(the upper pad 2 is corresponds with one pixel assembly) each of the at least one pixel assembly is die-bonded on a respective pad assembly, ([0064],die-bonding RGB LED chips 4 onto the substrate 1 by a die-bonding glue) and a periphery of each of the at least one the pad assembly in the respective accommodation cavity is a circular structure adapted to a bottom of the respective accommodation cavity. (Fig. 5, shows that from the top view the metal holes are circular.)
Regarding claim 11, Li further discloses:
the substrate is provided with a conductive hole penetrating through the upper surface of the substrate and the lower surface of the substrate, (See, Fig. 7, the substrate 1 has a metal hole 3 that goes from the upper surface of substrate 1 to the lower surface) and a pad assembly of the at least one pad assembly and a pin assembly (annotated Fig. 8a, pin assembly 31) of the at least two pin assemblies are electrically connected to each other by the conductive hole;(upper pad 2 is connected to the metal hold 3 the pin assembly 31 would be on the upper pad 2 and would be electrically connected to pin assembly 32)
the lower surface of the substrate is divided into an insulating region (annotated Fig. 8a, insulating region 10a)and a non-insulating region; (annotated Fig. 8a, non-insulating region 10b) and
the pin assembly (annotated Fig. 8a, pin assembly 31) further comprises a pin wire configured to connect a pin of the at least two pins to the conductive hole, (the pin is disposed in the non-insulating region, (in order to be electrically connected it would need to be in a non-insulating region) the insulating region is covered with solder resist ink, and the solder resist ink covers the pin wire in the insulating region. (wire 401)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Li as applied to claim 7 above, and further in view of Hussell US 20190371974 A1 (hereinafter Hussell).
Regarding claim 8, Li discloses all the elements of claim 7 above.
Li further discloses:
an accommodation cavity is filled with an encapsulant (protective layer 8),
Li does not appear to disclose, “the encapsulant is transparent and black.”
Hussell, which teaches an LED device which includes an encapsulate and with one or more electric traces to interconnect LEDS with each other (Hussell, Abstract), discloses:
the encapsulant is transparent and black (Hussell, Fig. 1, [0069] encapsulant layer 140 can be multiple layers that can be a transparent encapsulant with includes a white layer followed by a black layer.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Li to have the encapsulant is transparent and black as taught by Hussell for purposes of controlling light output of the LED device. (Hussell, [0069].)
Regarding claim 9, Li discloses all the elements of claim 7 above.
Li discloses:
an accommodation cavity is filled with an encapsulant,(Li, Fig. 7, protective layer 8)
Li does not appear to disclose that “the encapsulant comprises a first encapsulant layer at a lower portion of the accommodation cavity and a second encapsulant layer at an upper portion of the accommodation cavity, wherein the first encapsulant layer is transparent, and the second encapsulant layer is transparent and black.”
Hussell, which teaches an LED device which includes an encapsulate and with one or more electric traces to interconnect LEDS with each other (Hussell, Abstract), discloses:
the encapsulant (Hussell, Fig. 1, encapsulant 140) comprises a first encapsulant layer at a lower portion of the accommodation cavity and a second encapsulant layer at an upper portion of the accommodation cavity, wherein the first encapsulant layer is transparent, and the second encapsulant layer is transparent and black. (Hussell, Fig. 1, [0069] encapsulant layer 140 can be multiple layers that can be a transparent encapsulant with includes a white layer followed by a black layer.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Li to have the encapsulant comprises a first encapsulant layer at a lower portion of the accommodation cavity and a second encapsulant layer at an upper portion of the accommodation cavity, wherein the first encapsulant layer is transparent, and the second encapsulant layer is transparent and black as taught by Hussell for purposes of controlling light output of the LED device. (Hussell, [0069].)
Claims 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Jeon US 20230207481 A1 (hereinafter Jeon).
Regarding claim 12, Li discloses:
A light-emitting diode (LED) display device, (Li, [0004] a surface-mounted RGB LED packaging module) wherein the LED display device (Li, Figs.3-8b, surface mounted RGB LED packaging module) is formed by cutting ([0015] step 5: cutting the substrate into LED units) the LED display device array according to claim 1 along the cutting line (Fig. 8a, cutting line 7), and
the LED display device comprises:
a substrate (Fig. 8a, substrate 1) having an upper surface (Fig. 7, top of substrate 1) and a lower surface, (bottom of substrate 1) wherein the upper surface comprises a wiring region (annotated Fig. 8a, non-insulating region 10b) and a non-wiring region; (annotated Fig. 8a, insulating region 10a)
a circuit assembly disposed on the upper surface of the substrate and comprising a metal wire (annotated Fig. 8a, electroplating circuits 6) and at least one pad (first pin from the first pin assembly 331) assembly that are connected to each other, wherein the metal wire is disposed in the wiring region, and the at least one pad assembly is disposed in the non-wiring region; (See Fig. 8a.)
a pin assembly (pad labeled 4 on Fig. 7) disposed on the lower surface of the substrate and connected to the circuit assembly through a conductive hole (Fig. 7, lower pad 5) penetrating through the substrate; (See Fig. 7.)
at least one RGB chip group (RGB LED chips 4) correspondingly disposed on the at least one pad assembly respectively; and (Fig. 8a, the RGB LED chips are disposed on the upper pad 2.)
Li does not appear to disclose:
a metal identifier used for identifying a position of the at least one RGB chip group in the substrate, fixed in the non-wiring region, and connected to the metal wire by a connecting metal wire.
Jeon, which semiconductor packaging which use metal alignment marks on a solder resister layer of a printed circuit bord (PCB) to help attach semiconductor chips to a PCB (See Jeon, [0002]-[0003]), discloses:
a metal identifier used for identifying a position of the at least one RGB chip group in the substrate, (Jeon, Fig. 2, alignment marks AMK2 which provide alignment for other features. [0064] AMK2 is made of the same material as AMK2 which is a metal -see [0062].) fixed in the non-wiring region, and connected to the metal wire by a connecting metal wire. (The alignment markers AMK2 are connection by circuit line CLI which is shown to be made of the same material.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Li to have a metal identifier used for identifying a position of the at least one RGB chip group in the substrate, fixed in the non-wiring region, and connected to the metal wire by a connecting metal wire as taught by Jeon for purposes of preventing misalignment of different parts of the device that are to be connected on a single package.
Regarding claim 18, Li discloses:
A display panel, ([0002] Surface Mounted Device for LED displays) comprising a light-emitting diode (LED) display device, (Li, [0004] a surface-mounted RGB LED packaging module wherein the LED display device is formed by cutting ([0015] step 5: cutting the substrate into LED units) the LED display device array according to claim 1 along the cutting line; (Fig. 8a, cutting line 7), and
the LED display device comprises:
a substrate (Fig. 8a, substrate 1) having an upper surface (Fig. 7, top of substrate 1) and a lower surface, (bottom of substrate 1) wherein the upper surface comprises a wiring region (annotated Fig. 8a, non-insulating region 10b) and a non-wiring region; (annotated Fig. 8a, insulating region 10a)
a circuit assembly disposed on the upper surface of the substrate and comprising a metal wire (annotated Fig. 8a, electroplating circuits 6) and at least one pad (first pin from the first pin assembly 331) assembly that are connected to each other, wherein the metal wire is disposed in the wiring region, and the at least one pad assembly is disposed in the non-wiring region; (See Fig. 8a.)
a pin assembly (pad labeled 4 on Fig. 7) disposed on the lower surface of the substrate and connected to the circuit assembly through a conductive hole (Fig. 7, lower pad 5) penetrating through the substrate; (See Fig. 7.)
at least one RGB chip group (RGB LED chips 4) correspondingly disposed on the at least one pad assembly respectively; and (Fig. 8a, the RGB LED chips are disposed on the upper pad 2.)
Li does not appear to disclose:
a metal identifier used for identifying a position of the at least one RGB chip group in the substrate, fixed in the non-wiring region, and connected to the metal wire by a connecting metal wire.
Jeon, which semiconductor packaging which use metal alignment marks on a solder resister layer of a printed circuit bord (PCB) to help attach semiconductor chips to a PCB (See Jeon, [0002]-[0003]), discloses:
a metal identifier used for identifying a position of the at least one RGB chip group in the substrate, (Jeon, Fig. 2, alignment marks AMK2 which provide alignment for other features. [0064] AMK2 is made of the same material as AMK2 which is a metal -see [0062].) fixed in the non-wiring region, and connected to the metal wire by a connecting metal wire. (The alignment markers AMK2 are connection by circuit line CLI which is shown to be made of the same material.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Li to have a metal identifier used for identifying a position of the at least one RGB chip group in the substrate, fixed in the non-wiring region, and connected to the metal wire by a connecting metal wire as taught by Jeon for purposes of preventing misalignment of different parts of the device that are to be connected on a single package.
Claims 14 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Li and Jeon as applied to claim 12 above, and further in view of Dzyubenko et al. US 20230246003 A1 (hereinafter Dzyubenko).
Regarding claim 13, Li and Jeon disclose all the elements of claim 12.
Li and Jeon do not appear to disclose:
further comprising a black ink layer, wherein the black ink layer is disposed on the upper surface of the substrate and covers the metal wire and the connecting metal wire.
Dzyubenko, which teaches Light-emitting devices including solid-state light-emitting devices, light-emitting diodes (LEDs), and LED packages (Dzyubenko, Abstract), discloses:
further comprising a black ink layer, wherein the black ink layer is disposed on the upper surface of the substrate and covers the metal wire and the connecting metal wire. (Fig. 2, [0079], laminate film 28 which may be opaque and have black pigments in order to provide increased contrast to between the LED chips.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Li as modified by Jeon to have a black ink layer, wherein the black ink layer is disposed on the upper surface of the substrate and covers the metal wire and the connecting metal wire as taught by Dzyubenko for purposes of increasing contrast between the LED chips. (Dzyubenko, [0079].)
Regarding claim 14, Li and Jeon disclose all the elements of claim 12.
Li further discloses:
each of the at least one RGB chip group comprises a red LED chip, a green LED chip, and a blue LED chip, (RGB LED chips 4 would include a red LED (R), a green LED (G), and a blue LED (B).)
Li and Jeon to not appear to disclose explicitly, “wherein each of the red LED chip, the green LED chip, and the blue LED chip is a flip chip.”
Dzyubenko, which teaches Light-emitting devices including solid-state light-emitting devices, light-emitting diodes (LEDs), and LED packages (Dzyubenko, Abstract), discloses:
each of the red LED chip, the green LED chip, and the blue LED chip is a flip chip. (Fig. 2, chips 18-1 to 18-3 are LED of different wavelengths which can include a red wavelength a green wavelength and blue wavelength [0052]. Furthermore the LED chips can have any useful geometry including being flip-chip mounted.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Li as modified by Jeon to have each of the red LED chip, the green LED chip, and the blue LED chip is a flip chi as taught by Dzyubenko for purposes of in order to practice the invention of Li as modified by Jeon. Furthermore, to the extent understood by the Examiner, there is no evidence of criticality of the LEDs being flip chip in the specification.
Regarding claim 16. Li, Jeon, and Dzyubenko, disclose all the elements of claim 14.
Li further discloses:
the conductive hole (metal hole 3) comprises a common-electrode conductive hole, the common-electrode conductive hole is connected to electrodes of same polarity of all chips in the at least one RGB chip group by the metal wire and the pad assembly. (See Fig. 8a, all the chips in the RGB LED chips 4 are wired to a first pin assembly 311 in the upper pad 2.)
Regarding claim 17, Li, Jeon, and Dzyubenko, disclose all the element of claim 16.
Jeon further discloses:
wherein the metal identifier is connected to the common-electrode conductive hole by the connecting metal wire. (See Jeon, Fig. 2, the end of the circuit line CLI has a conductive hole that is connected by the wire portion of the CLI.)
Allowable Subject Matter
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 15, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a LED display device comprising each of the at least one pad assembly comprises three pairs of pads, the three pairs of pads are correspondingly connected to the red LED chip, the green LED chip, and the blue LED chip respectively, two pads in each pair of pads are axisymmetrically disposed, and midlines of the two pads in the each pair are on a same straight line.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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