DETAILED CORRESPONDENCE
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species D, Figs. 5a-5c, in the reply filed on 07/28/2026 is acknowledged.
Applicants designated claims 1-3 and 8-9 reads into elected Species D.
Claims 4-7 remain withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species A-C and E-F, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/28/2026.
Claim Objections
Claim 1 is objected to because of the following informalities: “a micro chamber is formed between the first chamber portion and the second chamber” should be “a micro chamber is formed between the first chamber portion and the second chamber portion”.
Furthermore, “the semiconductor wafer” and is referred to numerous times. It should be “the one or more stacked semiconductor wafers”. (Claims 4-7 are not examined but having similar issues).
Appropriate correction is required.
Claim Interpretations
The ” the outer edge surface micro-processing space is annular, and the outer edge surface micro-processing space is sealed and connects to the outside via the outer edge surface processing through-holes” of claim 3, Applicants’ Specification describes “the protruding edge 112 may mate with the indentation 122 and form a sealed micro chamber between the first chamber board 111 and the second chamber board 121” ([0037]), and will be examined accordingly. Specifically, there is no requirement of sealing between the micro chamber 130 and the internal micro-processing space 140.
The ” the semiconductor wafer can be transferred into or out of the micro chamber”, the wafer is not part of the apparatus. An apparatus that is capable of accommodate a wafer having a size fitting the claimed requirement is considered read into the claim.
It has been held that claim language that simply specifies an intended use or field of use for the invention generally will not limit the scope of a claim (Walter, 618 F.2d at 769, 205 USPQ at 409; MPEP 2106). Additionally, in apparatus claims, intended use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim (In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963); MPEP2111.02). When the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent (In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977); MPEP 2112.01).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wen et al. (CN 2015108361430, from IDS, hereafter ‘430, published on 01/22/2016, US 20180350635, also from IDS, is cited as English translation of ‘430).
‘430 teaches all limitations of:
Claim 1: Semiconductor Processing Apparatus And Method (title, is the claimed “A semiconductor processing device, comprising”):
As shown in FIG. 1a, semiconductor processing apparatus 100 includes an upper chamber portion 110 and a lower chamber portion 120 ([0051], last sentence), Upper chamber portion 110 may be movable relative to lower chamber portion 120 between an open position and a closed position ([0053], includes the claimed “a first chamber portion; a second chamber portion movable relative to the first chamber portion between an open position and a closed position”, note other Figures read into claim 1 too),
When upper chamber portion 110 is in the closed position relative to lower chamber portion 120, first protruding edge 112 may mate with first indentation 122 and form a sealed micro chamber between upper chamber board 111 and lower chamber board 121 ([0053], 3rd sentence, includes the claimed “wherein when the second chamber portion is in the closed position relative to the first chamber portion, a micro chamber is formed between the first chamber portion and the second chamber portion”),
As shown in FIGS. 1a, 1b and 1c, a semiconductor wafer 200 may be housed or accommodated in the micro chamber when upper chamber portion 110 is in the closed position relative to lower chamber portion 120 ([0056], includes the claimed “one or more stacked semiconductor wafers can be accommodated in the micro chamber”, see also illustration 1 below),
When the second chamber portion is in the open position relative to the first chamber portion, the micro chamber is configured for the semiconductor wafer to be transferred into or out of the micro chamber ([0007], 5th sentence, includes the claimed “and when the second chamber portion is in the open position relative to the first chamber portion, the semiconductor wafer can be transferred into or out of the micro chamber”),
As shown in FIGS. 5a-5c, 4a and 4b, upper chamber portion 410 may include an upper chamber board 411, a first protruding edge 412, a first internal surface 413 that faces the micro chamber, a second indentation 414, a second protruding edge 415 disposed between first internal surface 413 and second indentation 414, and a channel 416 located in a central region of first internal surface 413 ([0062], 6th sentence, Fig. 3a or Fig. 5a shows a bottom view of the upper chamber portion 410, the second indentation 414 is annular, note 414 label in Fig. 4a, the claimed “the first chamber portion has an internal surface facing the micro chamber”),
second through-hole 126 may include a second buffering mouth portion 126a and a second through-hole portion 126b (Fig. 2e, to [0058], 5th sentence, as the second through-hole 126 is connected with 414, includes the claimed “and the second chamber portion has an internal surface facing the micro chamber“ and “when the second chamber portion is in the closed position relative to the first chamber portion and the semiconductor wafer is housed in the micro chamber, the internal side surface of the first chamber portion at least abuts on an edge portion of a first side surface of the semiconductor wafer close to the first chamber portion, while the internal side surface of the second chamber portion at least abuts on an edge portion of a second side surface of the semiconductor wafer close to the second chamber portion, an outer edge surface micro-processing space located outside the semiconductor wafer is formed between the internal surface of the first chamber portion and the internal surface of the second chamber portion,” as shown in illustration below),
the processing fluid may flow through second through-hole 126 and be extracted ([0056], 2nd last sentence, includes the claimed “and the outer edge surface micro-processing space connects with the outside via outer edge surface processing-holes, and fluid flows in or out of the outer edge surface micro-processing space through the outer edge surface processing-hole”).
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[AltContent: connector][AltContent: arrow][AltContent: textbox (Using a larger wafer
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Claim 8: As illustrated in FIGS. 2a-2f, lower chamber portion 120 may have a recessed groove 124 formed on an internal surface 123 (which faces the micro chamber) of lower chamber portion 120 ([0055], includes the claimed “wherein: the second chamber portion comprises recess formed on the internal surface of the second chamber portion facing the micro chamber, the recess is located inside the outer edge surface micro-processing space” and as shown in Fig. 2e, other figures, such as Fig. 8a, has recess 823);
A surface (i.e., a lower surface) of semiconductor wafer 200 may abut against internal surface 123, on which recessed groove 124 is formed. Recessed groove 124 may thus be blocked or otherwise sealed by the surface of semiconductor wafer 200 to form a closed channel ([0056], 2nd sentence), The closed channel may be connected to the outer side of lower chamber portion 120 via first through-hole 125 and second through-hole 126 ([0056], 4th sentence, includes the claimed “when the second chamber portion is in the closed position relative to the first chamber portion and the semiconductor wafer is housed in the micro chamber, one side surface of the semiconductor wafer close to the second chamber part covers the top of the recesses to form an internal micro-processing space, which connects to the outside via internal processing-holes, and fluid flows in or out of the internal micro-processing space through the internal processing through-hole”, see also Figs. 8a and 9a for extra through-holes at the outer side of the through-holes 825 or 925).
Claim 9: First through-hole 824 may be used as an inlet for a fluid, whereas second through-hole 825 may be used as an outlet for the fluid. In other embodiments, first through-hole 824 may be used as the outlet for the fluid, whereas second through-hole 825 may be used as the inlet for the fluid. Obviously, both first through-hole 824 and second through-hole 825 are connected to the fluid processing space (Fig. 8a, [0077], last two sentences), second through-hole 825 may include a plurality of second through-holes even distributed in the peripheral region of integral recess 823 ([0076], Fig. 8a shows other through-holes outside of the through holes 825, includes the claimed “one or more of the internal processing through-holes are used as fluid inlets, while one or more of the internal processing through holes are used as fluid outlets, and the internal micro-processing space is sealed, which is connected to the outside via the internal processing through-holes”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over ‘430, as being applied to claim 1 rejection above, in view of Talieh et al. (US 20020029978, hereafter ‘978).
‘430 teaches some limitations of:
Claim 2: the illustration above shows the claimed “wherein an outer edge surface of the semiconductor wafer is exposed to the outer edge surface micro-processing space”,
After processing at least the partial area of the surface of semiconductor wafer 200, the processing fluid may flow through second through-hole 126 and be extracted ([0056], 2nd last sentence, includes the claimed “while one or more of the outer edge surface processing through-holes are used as fluid outlets.
Claim 3: the illustration above shows the claimed “the outer edge surface micro-processing space is annular”,
After processing at least the partial area of the surface of semiconductor wafer 200, the processing fluid may flow through second through-hole 126 and be extracted ([0056], 2nd last sentence, includes the claimed “and the outer edge surface micro-processing space connects to the outside via the outer edge surface processing through-holes”).
‘430 teaches ‘430 does not teach only one through-hole 126b at the edge portion and the other limitations of:
Claim 2: and one or more of the outer edge surface processing through-holes are used as fluid inlets.
Claim 3: (the outer edge surface micro-processing space is annular, and the outer edge surface micro-processing space) is sealed and (connects to the outside via the outer edge surface processing through-holes).
‘978 is analogous art in the field of a method and apparatus for electro-plating a metal on a semiconductor substrate ([0001]), etch a metal layer from the periphery of the workpiece (abstract). ’978 teaches that The liquid conductor is pumped from the reservoir 20 using a conventional pump (not shown) through an inlet channel 22 and injected into a liquid chamber 24. More than one pump may be used to pump the liquid conductor into the liquid chamber 24 when multiple reservoirs are used (Fig. 2, [0031, last two sentences), the liquid conductor in the liquid chamber 24 is removed via an outlet channel 25 to the reservoir 20 or a recycling reservoir (not shown) ([0036]), the present invention may be used to dissolve a Cu seed layer or spurous Cu films at the wafer edge 7 or at any portion of the wafer that is enclosed by chamber 24, or any portion of the wafer between the seal 14 and another seal (not shown) on the wafer backside 6 ([0041], last sentence), for the purpose of uniform plating or etching ([0005], [0017]).
Before the effective filling date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have added a seal along with inlet and outlet lines to the mouth portion 126a of ‘430, for the purpose of uniform plating or etching ([0005], [0017]).
In case Applicants argue that the second through-hole 126 is not necessarily annular, it would have been obvious to arrange the through-hole 126 as annular for complete exposure of the edge of the wafer to the processing fluid. Note also Fig. 4A of ‘978 also shows chamber 24 is annular.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20190071212, Fig. 7 does not show any marking of holes 252 nor discussion associated with Fig. 7. US 6001182 is cited for using non-standard wafer size (col. 3, lines 27-28). US 20020062848 is cited for fluid channel 238, 241 (Fig. 5) directly into microchamber (Fig. 6 shows wafer insider microchamber). US 20110146901 is cited for wafer a thickness of less than 100 micrometers ([0003]) to thicknesses of over 200 micrometers ([0005]). CN 2015108289298, from IDS, is cited for circular shaped groove 12 ([0070) and groove 24 ([0075]), and the groove is also annular (Fig. 11).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEATH T CHEN whose telephone number is (571)270-1870. The examiner can normally be reached 8:30am-5:00 pm.
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/KEATH T CHEN/Primary Examiner, Art Unit 1716
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