DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 -8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “rectifier circuit” is described as being a transistor ¶[0018] in Claim 2. The limitation that the rectifier circuit is a transistor is unclear to the examiner. This statement in claims is false and inaccurate because a circuit is not a transistor. A rectifier circuit is a well know term in the art with a well know definition that can not be overwritten. The rectifier circuit commonly defined as an electrical circuit that converts Alternating Current into Direct Current. The term rectifier circuit used in the claims of the instant application is confusing because the definition of a rectifier circuit commonly know in the art and the definition of rectifier circuit in the claims of the instant application are not the same. For purposes of examination the rectifier circuit is being taken as a transistor even though that is not consistent with the commonly known definition.
Note: The dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 11 is rejected under 35 U.S.C. 102 (A)(1) as being anticipated by Sasaki(JP2005136028).
Regarding Claim 1, FIG 4 discloses a semiconductor device comprising:
a first gate electrode (FIG 4; BGx and BGb (bottom gate); ¶ [0023]);
a first gate insulating film (FIG 4; 16; ¶[0024]) arranged on the first gate electrode (FIG 4; BGx and BGb (bottom gate); ¶ [0023]);
a semiconductor film (FIG 4; 11a and 11b; ¶[0024]) arranged on the first gate insulating film (FIG 4; 16; ¶[0024]) and overlapping the first gate electrode (FIG 4; BGx and BGb (bottom gate); ¶ [0023]);
a first terminal (FIG 4; 13a and 12b; ¶[0024]) in contact with the semiconductor film (FIG 4; 11a and 11b; ¶[0024]) and electrically connected to the semiconductor film (FIG 4; 11a and 11b; ¶[0024]) and the first gate electrode (FIG 4; BGx and BGb (bottom gate); ¶ [0023]);
a second terminal (FIG 4; 12a and 13b; ¶[0024]) in contact with the semiconductor film (FIG 4; 11a and 11b; ¶[0024]) and spaced apart from the first terminal (FIG 4; 13a and 12b; ¶[0024]);
a second gate insulating film (FIG 4; 14a, 14b and 15; ¶[0024]) arranged over the semiconductor film (FIG 4; 11a and 11b; ¶[0024]), the first terminal (FIG 4; 13a and 12b; ¶[0024]) and the second terminal (FIG 4; 12a and 13b; ¶[0024]); and
a second gate electrode (FIG 4; TGa and TGb (top gate); ¶[0024]) arranged on the second gate insulating film (FIG 4; 14a, 14b and 15; ¶[0024]), overlapping the semiconductor film FIG 4; 11a and 11b; ¶[0024]) and electrically connected to the second terminal (FIG 4; 12a and 13b; ¶[0024]).
Regarding Claim 2, FIG 4 discloses in ¶[0023], ¶[0024], ¶[0026] The semiconductor device according to claim 1, further comprising:
a first rectifier circuit (FIG 4; Tr20a; ¶[0036]); and
a second rectifier circuit (FIG 4; Tr20b; ¶[0036]),
wherein either one of the first rectifier circuit or the second rectifier circuit is a diode-connected first transistor (¶[0026]; diode connected), the other of the first rectifier circuit or the second rectifier circuit is a diode-connected second transistor (¶[0026]; diode connected),
the first transistor (Tr20a; ¶[0036]) includes the first gate electrode (FIG 4; BGx (bottom gate); ¶[0023]), the first gate insulating film (FIG 4; 16; ¶[0024] ), the semiconductor film (FIG 4; 11; ¶[0024]), the first terminal (FIG 4; 13a; ¶[0024]) and the second terminal (FIG 4; 12a; ¶[0024]), and
the second transistor (Tr20b; ¶[0036]) includes the second gate electrode (FIG 4; TGb; ¶[0024]), the second gate insulating film (FIG 4b; 16; ¶[0024]), the semiconductor film, the first terminal (FIG 4; 13b; ¶[0024]) and the second terminal (FIG 4; 12b; ¶[0024]).
Regarding Claim 3, FIG 4 discloses the semiconductor device according to claim 2, wherein the first terminal is a source electrode (FIG 4; 12a; ¶[0024]) in the first rectifier circuit (FIG 4; Tr20a; ¶[0036]), the second terminal is a drain electrode (FIG 4; 13a; ¶[0024]) in the first rectifier circuit (FIG 4;Tr20a; ¶[0036]),
the second terminal is a source electrode (FIG 4; 12b; ¶[0024]) in the second rectifier circuit (FIG 4; Tr20b; ¶[0036]), and the first terminal is a drain electrode (FIG 4; 13b; ¶[0024]) in the second rectifier circuit (FIG 4; Tr20b; ¶[0036]).
Regarding Claim 4, FIG 4 discloses the semiconductor device according to claim 2, wherein the semiconductor film includes a channel region (FIG 4; 11; ¶[0024]) of the first transistor (FIG 4; Tr20a; ¶[0036]) and a channel region (FIG 4; 11; ¶[0024]) of the second transistor (FIG 4; Tr20b; ¶[0036]) between the first terminal (FIG 4; 13a and 12b; ¶[0024]) and the second terminal (FIG 4; 12a and 13b; ¶[0024]) in a plan view,
the first gate insulating film (FIG 4; 16; ¶[0024]; lower gate insulating film) overlaps the first gate electrode (FIG 4; BGa and BGb (bottom gate); ¶ [0023]) in the channel region (FIG 4; 11; ¶[0024]) of the first transistor ((FIG 4; Tr20a; ¶[0036]), and the second gate insulating film (FIG 4; 16; ¶[0024]) overlaps the second gate electrode (FIG 4; TGa and TGb (top gate)) in the channel region (FIG 4; 11; ¶[0024]) of the second transistor (Tr20b; ¶[0036]).
Regarding Claim 5, FIG 4 discloses The semiconductor device according to claim 4, wherein a position of the channel region (FIG 4; 11; ¶[0024]) of the first transistor (FIG 4; Tr20a; ¶[0036]) is the same as a position of the channel region (FIG 4; 11; ¶[0024]) of the second transistor (FIG 4; Tr20b; ¶[0036]).
Regarding Claim 6, The semiconductor device according to claim 4, wherein the semiconductor film includes a first resistance region (FIG 4 with annotations; first resistance region) in which the first gate electrode (FIG 4; BGx; ¶ [0023]) does not overlap between the channel region (FIG 4; 11; ¶[0024]) of the first transistor (FIG 4; Tr20a; ¶[0036]) and the second terminal (FIG 4; 12a and 13b; ¶[0024]) in a plan view, and
a second resistance region (FIG 4 with annotations; second resistance region) in which the second gate electrode (FIG 4; TGa and TGb; ¶[0024]) does not overlap between the channel region (FIG 4; 11; ¶[0024]) of the second transistor (FIG 4; Tr20b; ¶[0036]) and the first terminal (FIG 4; 12b; ¶[0024]) in a plan view.
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Regarding Claim 11, FIG 4, ¶[0024] and ¶[0045] discloses a semiconductor integrated circuit comprising:
the semiconductor device according to claim 1, and an electronic device (FIG 6 and FIG 7; image reading apparatus; photo sensor (PS); ¶[0045]) electrically connected to the semiconductor device (FIG 4; Tr20a and Tr20b; ¶[0036]).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki(JP2005136028) as applied to claim 1-6 and 11 above, and further in view of Yamazaki(JP5587591B2).
Regarding Claim 7, Sasaki teaches the semiconductor device according to claim 6,
Sasaki teaches wherein the position of the channel region of the first transistor is different from the position of the channel region of the second transistor.
Yamazaki teaches in FIG 1(A) wherein the position of the channel region (FIG 1(A); 405) of the first transistor (FIG 1(A); 430) is different from the position of the channel region (FIG 1(A); 407) of the second transistor (FIG 1(A); 431).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Sasaki, a semiconductor device with two terminals, and the prior art of Yamazaki, a semiconductor device with multiple transistors with channel regions in different positions. This combination would produce a semiconductor device with multiple transistors with two terminals and channel regions with different positions. The position of the channel region in a transistor determines the electron mobility pathway, influencing the electrical characteristic and reliability of the semiconductor device Yamazaki(¶[0022]).
Regarding Claim 8, Sasaki and Yamazaki teaches the semiconductor device according to claim 7.
Sasaki teaches in FIG 4, wherein the semiconductor film includes amorphous silicon (FIG 4; 11; ¶[0024]; channel region made of amorphous silicon), polycrystalline silicon or metal oxide.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki(JP2005136028) as applied to claim 1-6 and 11 above, and further in view of Oikawa(US8999836B2).
Regarding Claim 9, Sasaki teaches a display device comprising:
the semiconductor device according to claim 1;
Sasaki does not teach
a display section including a plurality of pixels electrically connected to the plurality of semiconductor devices; and
a control circuit electrically connected to the plurality of pixels and controlling the plurality of pixels.
Oikawa teaches in FIG 16A, FIG 23 and Col 39
a display section including a plurality of pixels (FIG 16A; 2702; Col 5 Ln 16-19) electrically connected to the plurality of semiconductor devices (Switch elements; TFT; Col 5 Ln 30-32); and
a control circuit (FIG 23; 707; Col 39 Ln 17-21) electrically connected to the plurality of pixels (FIG 23; 702) and controlling the plurality of pixels (FIG 23; 707; Col 39 Ln 17-21).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Sasaki, a semiconductor device with two terminals, and the prior art of Oikawa, as semiconductor device containing a display area with a control circuit electrically connected to the plurality of pixels and controlling the plurality of pixels. This combination produces a semiconductor device with two terminals containing a display area with a control circuit electrically connected to the plurality of pixels and controlling the plurality of pixels. Control circuit outputs signal into the scanning line side and the signal line side Oikawa(FIG 23; 707; Col 39 Ln 19-21). The scanning line driver circuit is connected to the pixel portion containing the plurality of pixels as shown in Oikawa(FIG 16B; 3702 scanning line driver circuit and 3701 pixel portion). The signal output for the control circuit controls the plurality of pixels allowing the logical pathway of the electrical connections to be managed.
Regarding Claim 10, Sasaki the display device according to claim 9,
Sasaki does not teach wherein the control circuit is electrically connected to the semiconductor device.
Oikawa teaches in FIG 16, FIG 17 and FIG 23 wherein the control circuit is electrically connected to the semiconductor device (FIG 23; 707; Col 39 Ln 19-21) (FIG 17A; 701 (pixel portion) and
(FIG 16B; 3702 scanning line driver circuit and 3701 pixel portion).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the prior art of Sasaki, a semiconductor device with two terminals, and the prior art of Oikawa, as semiconductor device containing a display area with a control circuit electrically connected to a semiconductor device. This combination would produce a semiconductor device with two terminals with a display area containing a control circuit electrically connected. Control circuit outputs signal into the scanning line side and the signal line side Oikawa(FIG 23; 707; Col 39 Ln 19-21). The scanning line driver circuit is connected to the pixel portion in Oikawa(FIG 16B; 3702 scanning line driver circuit and 3701 pixel portion), and the pixel portions are connected to the semiconductor devices (TFT). Electrically connecting the control circuit to the semiconductor device can regulate the performance of the transistor based on the output of the control circuit.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s
disclosure:
Tada(US20180374875A1): This reference teaches a semiconductor device with a thin film transistor
Miyake(US8766253B2): This reference teaches a semiconductor device with a transistor with a oxide semiconductor material
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BASEEMAH QADEER RUCKER whose telephone number is (571)272-0380. The examiner can normally be reached Monday-Friday 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at 5712727925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.Q.R./ Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
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