DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
(1) Paragraph [0025] recites “Oxygenation is performed”…, “while not being transferred to high-k dielectric material 164 surrounding the nanosheets 122 of the bottom transistor 130”, which should be “while not being transferred to high-k dielectric material 164 surrounding the nanosheets 120 of the bottom transistor 130”.
(2) The first line of paragraph [0027] recites “As best seen in FIG. 1B” which should be “As best seen in FIG. 1C”.
Appropriate correction is required.
Claim Objections
Claims 11 and 20 objected to because of the following informalities:
Claim 11 recites “an oxygen vacancy in the high-k material of the second transistor is lower than the high-k material of the first transistor”. While the Examiner understands that an oxygen vacancy level is being compared between the second and first transistors, to ensure clarity, the limitation should be “an oxygen vacancy in the high-k material of the second transistor is lower than an oxygen vacancy in the high-k material of the first transistor”.
Appropriate correction is required.
Claim 20 recites “an oxygen vacancy in the high-k material of the second transistor is lower than the high-k material of the first transistor”. While the Examiner understands that an oxygen vacancy level is being compared between the second and first transistors, to ensure clarity, the limitation should be “an oxygen vacancy in the high-k material of the second transistor is lower than an oxygen vacancy in the high-k material of the first transistor”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-7, 12, and 14-18 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Lai; Pei Ying et al. (US 2024/0290630; hereinafter Lai).
Regarding claim 1, Lai discloses a semiconductor device (Figs 1A-1C, 2A-2J; ¶ [0019-54]) comprising:
stacked complementary transistors (14L and 14U; Fig 1A; ¶ [0019-32]; for example, 20L-2 and 20U-2; Figs 2A-2J; ¶ [0033]) comprising a high-k material (a high-k dielectric material, as described in ¶ [0037], which comprises 105A-105D; Fig 2J; ¶ [0036-51]; {78L-1,78U-1,78L-2,78U-2; Fig 1A; ¶ [0021-22,0031,0047-50]}), a common work function metal (80L-1,80U-2,80L-2,80-U2, comprising a same type of work function layer {e.g., n-metal or p-metal}; Fig 1A; ¶ [0031,0051]; 135; Fig 2J) and a gate conductor metal (metal fill {bulk} layer {80L-1,80U-2,80L-2,80-U2; Fig 1A}; ¶ [0031,0053]; and
a vertically stacked sidewall adjacent to the gate conductor metal, the vertically stacked sidewall comprising a first spacer (inner spacers 54; Fig 1A; ¶ [0021]) and a second spacer (gate spacers 44; Fig 1A; ¶ [0021]), the second spacer being stacked on the first spacer (layers 26 {L,M,U},17 therebetween);
wherein the high-k material is on an inner sidewall of the second spacer (for example, 78U-2 is on a side of 44 facing 80U-2; Fig 1A).
Regarding claim 3, Lai discloses the semiconductor device of claim 1, wherein the common work function metal (80L-1,80U-2,80L-2,80-U2; Fig 1A comprising 135; Fig 2J) is formed on the high-k material (78L-1,78U-1,78L-2,78U-2; Fig 1A) on the inner sidewall of the second spacer (44; Fig 1A) and is formed on an another inner sidewall of the first spacer (54; Fig 1A; as shown in Fig 1A, and associated description).
Regarding claim 4, Lai discloses the semiconductor device of claim 1, wherein the stacked complementary transistors (14L,14U; Fig 1A) are separated by a middle dielectric isolation layer (17; Fig 1A; ¶ [0025]).
Regarding claim 5, Lai discloses the semiconductor device of claim 1, wherein the first spacer (54; Fig 1A) extends above a bottom surface of a middle dielectric isolation layer (17; Fig 1A; transistor 14U comprises inner spacer 54 above 17, as shown in Fig 1A).
Regarding claim 6, Lai discloses the semiconductor device of claim 1, wherein the second spacer (44; Fig 1A) is above a bottom surface of a middle dielectric isolation layer (17; Fig 1A; gate spacer 44 is above 17, as shown in Fig 1A).
Regarding claim 7, Lai discloses the semiconductor device of claim 1, wherein the stacked complementary transistors (14L,14U; Fig 1A) are separated by a middle dielectric isolation layer (17, comprising, for example, silicon oxide; Fig 1A; ¶ [0025]), the middle dielectric isolation layer and the first spacer (54, comprising, for example, silicon oxide; Fig 1A; ¶ [0028]) comprising a same material.
Regarding claim 12, Lai discloses a method (Figs 6,7; ¶ [0078-90]) comprising:
forming stacked complementary transistors (14L and 14U; Fig 1A; ¶ [0019-32]; for example, 20L-2 and 20U-2; Figs 2A-2J; ¶ [0033]) comprising a high-k material (a high-k dielectric material, as described in ¶ [0035], which comprises 105A-105D; Fig 2J; ¶ [0036-51]; {78L-1,78U-1,78L-2,78U-2; Fig 1A; ¶ [0021-22,0031,0047-50]}), a common work function metal (80L-1,80U-2,80L-2,80-U2, comprising a same type of work function layer {e.g., n-metal or p-metal}; Fig 1A; ¶ [0031,0051]; 135; Fig 2J) and a gate conductor metal (metal fill {bulk} layer {80L-1,80U-2,80L-2,80-U2; Fig 1A}; ¶ [0031,0053]; and
providing a vertically stacked sidewall adjacent to the gate conductor metal, the vertically stacked sidewall comprising a first spacer (inner spacers 54; Fig 1A; ¶ [0021]) and a second spacer (gate spacers 44; Fig 1A; ¶ [0021]), the second spacer being stacked on the first spacer (layers 26{L,M,U},17 therebetween);
wherein the high-k material is on an inner sidewall of the second spacer (for example, 78U-2 is on a side of 44 facing 80U-2; Fig 1A).
Regarding claim 14, Lai discloses the method of claim 12, wherein the common work function metal (80L-1,80U-2,80L-2,80-U2; Fig 1A comprising 135; Fig 2J) is formed on the high-k material (78L-1,78U-1,78L-2,78U-2; Fig 1A) on the inner sidewall of the second spacer (44; Fig 1A) and is formed on an another inner sidewall of the first spacer (54; Fig 1A; as shown in Fig 1A, and associated description).
Regarding claim 15, Lai discloses the method of claim 12, wherein the stacked complementary transistors (14L,14U; Fig 1A) are separated by a middle dielectric isolation layer (17; Fig 1A; ¶ [0025]).
Regarding claim 16, Lai discloses the method of claim 12, wherein the first spacer (54; Fig 1A) extends above a bottom surface of a middle dielectric isolation layer (transistor 14U comprises inner spacer 54 above 17; Fig 1A).
Regarding claim 17, Lai discloses the method device of claim 12, wherein the second spacer (44; Fig 1A) is above a bottom surface of a middle dielectric isolation layer (17; Fig 1A; gate spacer 44 is above 17, as shown in Fig 1A).
Regarding claim 18, Lai discloses the semiconductor device of claim 12, wherein the stacked complementary transistors (14L,14U; Fig 1A) are separated by a middle dielectric isolation layer (17, comprising, for example, silicon oxide; Fig 1A; ¶ [0025]), the middle dielectric isolation layer and the first spacer (54, comprising, for example, silicon oxide; Fig 1A; ¶ [0028]) comprising a same material.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9, 11 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lai; Pei Ying et al. (US 2024/0290630; hereinafter Lai) in view of Cheng; Kangguo et al. (US 2013/0062704; hereinafter Cheng).
Regarding claim 8, Lai discloses the semiconductor device of claim 1, wherein: the stacked complementary transistors comprise a first transistor (14L; Fig 1A) and a second transistor (14U; Fig 1A).
Lai does not disclose the high-k material surrounding the second transistor comprises a higher amount of oxygen than the high-k material surrounding the first transistor.
However, Lai discloses a method of tuning the threshold voltages of the first and second transistors to be different from one another by providing the gate dielectrics with different compositions (¶ [0018, 0033-54]). In the same field of endeavor, Cheng discloses another method of tuning threshold voltages of a first (108; Fig 8; ¶ [0043]) and a second transistor (106; Fig 8; ¶ [0043]) to be different from one another by providing the gate dielectrics with different properties, namely by reducing oxygen vacancies in a high-k gate dielectric in the second transistor, providing the high-k gate dielectric of the second transistor with fewer oxygen vacancies and correspondingly higher oxygen content, than the high-k gate dielectric of the first transistor (¶ [0029]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the threshold voltages of Lai may be tuned in a similar manner of controlling an amount of oxygen in the high-k material of the first and second transistors respectively. One may have been motivated to do this as an alternate method to the dipole methods disclosed by Lai, and would have had a reasonable expectation of success because each of the methods are well-known in the art (Cheng; ¶ [0029]; Lai; ¶ [0017]).
Regarding claim 9, Lai in view of Cheng discloses the semiconductor device of claim 8, wherein a threshold voltage of the second transistor is different from a threshold voltage of the first transistor (as applied to claim 8; Cheng; ¶ [0029]).
Regarding claim 11, Lai in view of Cheng discloses the semiconductor device of claim 8, the first transistor and the second transistor comprise the high-k material (Cheng; the high-k dielectric material, as applied to claim 1); and an oxygen vacancy in the high-k material of the second transistor is lower than an oxygen vacancy in the high-k material of the first transistor (as applied to claim 8; Cheng; ¶ [0029]).
Regarding claim 19, Lai discloses the method of claim 12, wherein: the stacked complementary transistors comprise a first transistor (14L; Fig 1A) and a second transistor (14U; Fig 1A).
Lai does not disclose the high-k material surrounding the second transistor comprises a higher amount of oxygen than the high-k material surrounding the first transistor.
However, Lai discloses a method of tuning the threshold voltages of the first and second transistors to be different from one another by providing the gate dielectrics with different compositions (¶ [0018, 0033-54]). In the same field of endeavor, Cheng discloses another method of tuning threshold voltages of a first (108; Fig 8; ¶ [0043]) and a second transistor (106; Fig 8; ¶ [0043]) to be different from one another by providing the gate dielectrics with different properties, namely by reducing oxygen vacancies in a high-k gate dielectric in the second transistor, providing the high-k gate dielectric of the second transistor with fewer oxygen vacancies and correspondingly higher oxygen content, than the high-k gate dielectric of the first transistor (¶ [0029]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the threshold voltages of Lai may be tuned in a similar manner of controlling an amount of oxygen in the high-k material of the first and second transistors respectively. One may have been motivated to do this as an alternate method to the dipole methods disclosed by Lai, and would have had a reasonable expectation of success because each of the methods are well-known in the art (Cheng; ¶ [0029]; Lai; ¶ [0017]).
Regarding claim 20, Lai in view of Cheng discloses the semiconductor device of claim 19, wherein a threshold voltage of the second transistor is different from a threshold voltage of the first transistor (as applied to claim 19; Cheng; ¶ [0029]), wherein the first transistor and the second transistor comprise the high-k material (Lai; as applied to claims 19 and 12); and an oxygen vacancy in the high-k material of the second transistor is lower than an oxygen vacancy in the high-k material of the first transistor (as applied to claim 12; Cheng; ¶ [0029]).
Allowable Subject Matter
Claims 2, 10, and 13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein an another inner sidewall of the first spacer is free of the high-k material”. In the prior art Lai, a high-k material (high-k dielectric material, as described in ¶ [0037], which comprises layers 105A-105D {Fig 2J} of layers 80L1-U2 {Fig 1A}) is on an inner sidewall of the second spacer (54; Fig 1A), and 105A-105D comprise different compositions due to doping (¶ [0046]), but each of 105A-105D and the corresponding high-k material 78U-1 and 78-2 on another inner sidewall of the first spacer (44; Fig 1) comprise the same high-k dielectric material (330; Fig 6; for example, HfO2; ¶ [0037]). Additional prior art reviewed by the Examiner does not disclose or suggest the particular combination of limitations including all of the limitations of the base claim.
Regarding claim 10, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the higher amount of the oxygen in the high-k material surrounding the second transistor is relative to an oxygen vacancy in the high-k material on the inner sidewall of the second spacer”. The prior art Cheng discloses filling oxygen vacancies in a high-k gate dielectric by delivering oxygen from an adjacent oxide spacer (130; Fig 8; ¶ [0029,0043]); however, neither Cheng nor other prior art reviewed by the Examiner disclose or suggest the particular combination of limitations including all of the limitations of the base claim.
Regarding claim 13, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein an another inner sidewall of the first spacer is free of the high-k material”. In the prior art Lai, a high-k material (high-k dielectric material, as described in ¶ [0037], which comprises layers 105A-105D {Fig 2J} of layers 80L1-U2 {Fig 1A}) is on an inner sidewall of the second spacer (54; Fig 1A), and 105A-105D comprise different compositions due to doping (¶ [0046]), but each of 105A-105D and the corresponding high-k material 78U-1 and 78-2 on another inner sidewall of the first spacer (44; Fig 1) comprise the same high-k dielectric material (330; Fig 6; for example, HfO2; ¶ [0037]). Additional prior art reviewed by the Examiner does not disclose or suggest the particular combination of limitations including all of the limitations of the base claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ando; Takashi et al. (US 2022/0190167; the prior art discloses threshold voltage tuning by oxygen vacancy modification of a dielectric);
Lim; Ha-jin et al. (US 2017/0084711; the prior art discloses controlling an oxygen vacancy density in a work function layer to thereby implement devices having various threshold voltages);
Zhou; Huimei et al. (US 2021/0384139; the prior art discloses an oxygen diffusion block layer to control a threshold voltage shift due to oxygen vacancy level change in a gate dielectric due to oxygen diffusion or lack thereof).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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