CTNF 18/648,632 CTNF 82874 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s of U.S. Patent No. 11,973,052 . Although the claims at issue are not identical, they are not patentably distinct from each other because regarding claim 1, U.S. Patent No. 11,973,052 discloses 1, a packaged electronic device, comprising: a first semiconductor die having a first conductive plate; and a second semiconductor die having a second conductive plate and a conductive stud bump that extends outward from a planar side of the second conductive plate . Regarding claims 2-16, U.S. Patent No. 11,973,052 discloses in claims 2-10,17-20, a packaged electronic device further including: a conductive bond wire having a first end and a second end, the first end of the conductive bond wire bonded to a planar side of the first conductive plate; wherein the second end of the conductive bond is wire bonded to the conductive stud bump; wherein the first end of the conductive bond wire joined to the first conductive plate at a first angle to a plane of the planar side of the first conductive plate; wherein the first end of the conductive bond wire joined to the first conductive plate at a first angle to a plane of the planar side of the first conductive plate; wherein the second end is joined to the conductive stud bump at a second angle to the planar side of the second conductive plate; wherein the second end is joined to the conductive stud bump at a second angle to the planar side of the second conductive plate; wherein the first angle is greater than or equal to 60 degrees; wherein the first angle is greater than or equal to 60 degrees; wherein the second angle is greater than or equal to 60 degrees; wherein the second angle is greater than or equal to 60 degrees; wherein the second angle is less than or equal to 75 degrees; wherein the second angle is less than or equal to 75 degrees; wherein a first end of a conductive bond wire is bonded to a planar side of the first conductive plate by a ball bond, and a second end of the conductive bond wire is bonded to the conductive stud bump by a stitch bond; wherein the stitch bond of the second end joins half or less of the conductive stud bump; comprising a package structure that covers the first semiconductor die, the second semiconductor die, and the conductive stud bump. Regarding claim 17, U.S. Patent No. 11,973,052 discloses in claim 11, a method of manufacturing a packaged electronic device, the method comprising: fabricating a first semiconductor die having a first conductive plate; fabricating a second semiconductor die having a second conductive plate; attaching the first semiconductor die to a first die attach pad; attaching the second semiconductor die to a second die attach pad; and forming a conductive stud bump extending outward from a planar side of the second conductive plate. Regarding claims 18-25, U.S. Patent No. 11,973,052 discloses in claims 12-16, a method further including bonding a first end of a conductive bond wire to the first conductive plate; further including bonding a second end of the conductive bond wire to the conductive stud bump at an angle to a plane of a planar side of the second conductive plate; wherein the angle 60 degrees or more to the planar side of the second conductive plate; further including forming a package structure to cover the first semiconductor die, the second semiconductor die and the conductive stud bump; wherein: the conductive stud bump is formed using a wire bonding tool; a first end of the conductive bond wire is bonded to the first conductive plate using the wire bonding tool; and a second end of the conductive bond wire is bonded to the conductive stud bump using the wire bonding tool; wherein: bonding the first end of the conductive bond wire to the first conductive plate includes forming a ball bond to join the first end of the conductive bond wire to a planar side of the first conductive plate; and bonding the second end of the conductive bond wire to the conductive stud bump includes forming a stitch bond to join the second end of the conductive bond wire to the conductive stud bump; wherein the stitch bond of the second end joins half or less of the conductive stud bump; wherein the second angle is less than or equal to 75 degrees. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MARC - ANTHONY ARMAND Primary Examiner Art Unit 2813 /MARC-ANTHONY ARMAND/Primary Examiner, Art Unit 2813 Application/Control Number: 18/648,632 Page 2 Art Unit: 2813 Application/Control Number: 18/648,632 Page 3 Art Unit: 2813 Application/Control Number: 18/648,632 Page 4 Art Unit: 2813 Application/Control Number: 18/648,632 Page 5 Art Unit: 2813 Application/Control Number: 18/648,632 Page 6 Art Unit: 2813 Application/Control Number: 18/648,632 Page 7 Art Unit: 2813
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