Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 8-9 are objected to because of the following informalities: the limitation "a plurality of first bumps disposed between the circuit board and the first redistribution layer" in lines 2-3 of claim 8 and lines 2-3 of claim 9 are redundant and merely restate the same limitation of their parent claim, claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11, 13, and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20220399301 A1) in view of Kim '993 (US 20220084993 A1).
Regarding claim 1, Chang’s first embodiment discloses a semiconductor package (Fig. 6, 1e)
comprising: a first redistribution layer (portion of 13 beneath the upper surface of 162; see attached figure); a first semiconductor chip (20) disposed on the first redistribution layer; a circuit board (portion of 13 comprising wire bonding pads 14) disposed between the first redistribution layer and the first semiconductor chip; a plurality of bonding wires (51) connecting the first semiconductor chip and the circuit board to each other; a second redistribution layer (4) disposed on the first semiconductor chip; a second semiconductor chip (60) disposed on the second redistribution layer (shown). However, Chang’s first embodiment does not disclose a plurality of conductive posts connecting the first redistribution layer and the second redistribution layer to each other, or a plurality of first bumps disposed between the circuit board and the first redistribution layer.
On the other hand, Chang’s second embodiment discloses a plurality of conductive posts (Fig. 9, 80) connecting the first redistribution layer and the second redistribution layer to each other (Shown in fig. 9). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Chang’s first embodiment according to the teachings of Chang’s second embodiment such that the first and second redistribution layers would be connected by a plurality of conductive posts because of the structural support a conductive post provides in addition to forming electrical connections, especially when compared to bonding wires.
Chang still does not disclose a plurality of first bumps disposed between the circuit board and the first redistribution layer. Kim ‘993 discloses a plurality of first bumps (Fig. 1B, solder bumps 808) used to bond a circuit board (810) to a redistribution layer (2000). It would have been obvious to one of ordinary skill in the art before the time of effective filing to modify Chang according to the teachings of Kim ‘993 such that a plurality of first bumps would be disposed between the circuit board and the first redistribution layer as is common in the art in order to mitigate the mechanical strain between the circuit board and the first redistribution layer during mounting, and provide necessary space between the circuit board and the first redistribution layer to prevent electrical contact between their respective conductive layers.
Regarding claim 2, Chang’s second embodiment further discloses further comprising a plurality of external connection terminals (Fig. 9, 94) disposed under the first redistribution layer (Shown), wherein the second semiconductor chip is disposed on the second redistribution layer, in a flip-chip structure. (Shown in accordance with Fig. 1 of instant application).
Regarding claim 3, Chang’s first embodiment discloses wherein the plurality of bonding wires electrically connect an upper surface of the first semiconductor chip and an upper surface of the circuit board (Fig. 6 shows bonding wires 51 connecting the upper surface of chip 20 and the upper surface of the circuit board).
Regarding claim 4, Chang’s second embodiment discloses a plurality of second bumps disposed between the second semiconductor chip and the second redistribution layer (Fig. 9, bumps connecting second semiconductor chip 60 to second redistribution layer 4).
Regarding claim 5, Chang’s second embodiment disclose wherein a size of each of the plurality of first bumps is greater than a size of each of the plurality of second bumps (Shown in Fig. 9).
Regarding claim 6, Chang’s first embodiment further discloses a molding layer (Fig. 6, 31) disposed on the circuit board and encapsulating the first semiconductor chip and the plurality of bonding wires (Shown).
Regarding claim 7, Chang’s second embodiment further discloses a molding layer (Fig. 9, 31) disposed on the first redistribution layer and encapsulating the first semiconductor chip and the plurality of conductive posts (Shown).
Regarding claim 8, Kim ‘993 discloses a molding layer (Fig. 1B, 720) comprising a portion encapsulating a plurality of solder bumps (Shown). It would have been obvious to one of ordinary skill in the art before the time of effective filing to further modify Chang in view of Kim ‘993 such that Chang’s molding layer would comprise a portion for encapsulating the plurality of first bumps as taught by Kim ‘993 in order to provide support, protection and isolation of the solder bumps, as is common in the art.
Regarding claim 9, Kim ‘993 discloses an underfill layer (720) disposed between a chip (700) and a redistribution layer (1000) and encapsulating the plurality of first bumps (Shown). It would have be obvious to one of ordinary skill in the art before the time of effective filing of the invention to further modify Chang in view of Kim ‘993 such that an underfill layer would be disposed between Chang’s circuit board and first redistribution layer as to encapsulate the plurality of first bumps in order to provide support, protection and isolation of the solder bumps, as is common in the art.
Regarding claim 10, Chang’s first embodiment further discloses a molding layer (Fig. 6, 70) disposed on the second redistribution layer and encapsulating the second semiconductor chip (Shown).
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Regarding claim 11, Chang’s first embodiment discloses a semiconductor package (Fig. 6, 1e) comprising: a lower structure; an upper structure stacked on the lower structure (see attached figure), wherein the lower structure comprises: a circuit board (portion of 13 comprising wire bonding pads 14); wherein the lower structure comprises: a first redistribution layer (portion of 13 beneath the upper surface of 162; see attached figure); a first semiconductor chip (20) disposed on the first redistribution layer; a plurality of bonding wires (51) connecting the first semiconductor chip and the first redistribution layer to each other; wherein the upper structure comprises: a second redistribution layer (4) disposed on the lower structure; a second semiconductor chip (60) disposed on the second redistribution layer. However, Chang’s first embodiment does not disclose a plurality of external connection terminals disposed on the lower structure, the first redistribution layer being spaced apart from the circuit board, and a plurality of conductive posts connecting the first redistribution layer and the upper structure to each other and a plurality of bumps disposed between the second semiconductor chip and the second redistribution layer.
On the other hand, Chang’s second embodiment discloses a plurality of external connection terminals disposed under the lower structure (Fig. 9, 94). It would have been obvious to one of ordinary skill in the art before the effective time of filing of the invention to modify Chang’s first embodiment according to Chang’s second embodiment such that Chang’s first embodiment would further include a plurality of external connection terminals disposed under the lower structure as is extremely common in the art in order to allow the package to integrate into or be in communication with a larger system such as a computer, tablet, or cell phone.
Chang’s second embodiment further discloses a plurality of conductive posts (Fig. 9, 80) connecting the first redistribution layer and the upper structure to each other (Shown in Fig. 9) and a plurality of bumps disposed between the second semiconductor chip and the second redistribution layer (Fig. 9 shows bumps connecting chip 60 to second redistribution layer 4). It would have been obvious to one of ordinary skill in the art before the effective time of filing of the invention to modify Chang’s first embodiment according to Chang’s second embodiment such that Chang’s first embodiment would further include a plurality of conductive posts connecting the first redistribution layer and the upper structure to each other, and a plurality of bumps disposed between the second semiconductor chip and the second redistribution layer, due to the increased mechanical strength and therefore electrical reliability of connections such as pillars and solder bumps, especially when compared to alternatives such as bonding wires.
Chang still does not disclose a plurality of first bumps disposed between the circuit board and the first redistribution layer. Kim ‘993 discloses a plurality of first bumps (Fig. 1B, solder bumps 808) used to bond a circuit board (810) to a redistribution layer (2000). It would have been obvious to one of ordinary skill in the art before the time of effective filing to modify Chang according to the teachings of Kim ‘993 such that a plurality of first bumps would be disposed between the circuit board and the first redistribution layer and therefore the circuit board would be spaced apart from the first redistribution layer in order to mitigate the mechanical strain between the circuit board and the first redistribution layer during mounting, and provide necessary space between the circuit board and the first redistribution layer to prevent electrical contact between their respective conductive layers.
Regarding claim 13, Chang’s first embodiment discloses wherein the second semiconductor chip is disposed on the second redistribution layer in a flip-chip structure (Shown in Fig. 6).
Regarding claim 15, Chang’s first embodiment discloses wherein the lower structure further comprises a lower molding layer (Fig. 6, 31) disposed on the first redistribution layer and encapsulating the first semiconductor chip, the plurality of bonding wires, (Shown in fig. 6), and the upper structure further comprises an upper molding layer (70) disposed on the second redistribution layer and encapsulating the second semiconductor chip (Shown in fig. 6). However, Chang’s first embodiment does not disclose a lower molding layer encapsulating the plurality of conductive posts.
On the other hand, Chang’s second embodiment discloses a lower molding layer (Fig. 9, 31) encapsulating the plurality of conductive posts (Shown). It would have been obvious to one of ordinary skill in the art before the time of effective filing to modify Chang’s first embodiment according to the teachings of Chang’s second embodiment such that conductive posts would be disposed in the lower molding layer of Chang’s first embodiment in order to increase the mechanical strength and electrical reliability of the device by using rigid connections such as pillars and solder bumps, especially when compared to alternatives such as bonding wires.
Regarding claim 16, Chang’s second embodiment discloses wherein the upper structure further comprises an underfill layer disposed between the second semiconductor chip and the second redistribution layer and encapsulating the plurality of bumps (Fig. 9, portion of 70 disposed between second chip 60 and second redistribution layer 4 and encapsulating the bumps).
Regarding claim 17, Chang’s first embodiment a semiconductor package (Fig. 6, 1e)
comprising: a first redistribution layer (portion of 13 beneath the upper surface of 162; see attached figure); a first semiconductor chip (leftmost 20) and a second semiconductor chip (rightmost 20), spaced apart from each other in a first direction (X direction) on the first redistribution layer (Shown); a first circuit board (portion of 13 comprising the wire bonding pads 14 connected to first semiconductor chip) disposed between the first redistribution layer and the first semiconductor chip (Shown); a second circuit board (portion of 13 comprising the wire bonding pads 14 connected to second semiconductor chip) disposed between the first redistribution layer and the second semiconductor chip (Shown); first bonding wires (bonding wires 51 corresponding to first semiconductor chip) connecting the first semiconductor chip and the first circuit board to each other; second bonding wires (bonding wires 51 corresponding to second semiconductor chip) connecting the second semiconductor chip and the second circuit board to each other (Shown); a second redistribution layer (4) disposed on the first semiconductor chip; a third semiconductor chip (leftmost 60) and a fourth semiconductor chip (rightmost 60), spaced apart from each other in the first direction on the second redistribution layer (Shown); wherein the first semiconductor chip is connected to the first redistribution layer through the first bonding wires and the first circuit board (Shown), and the third semiconductor chip is attached to the second redistribution layer, in a flip-chip structure (Shown in accordance with Fig. 1 of the instant application). However, Chang’s first embodiment does not disclose a plurality of first bumps disposed on the first redistribution layer, wherein the first circuit board is disposed on a first set of the plurality of first bumps and the second circuit board is disposed on a second set of the plurality of first bumps, a plurality of second bumps disposed on the second redistribution layer, wherein the third semiconductor chip is disposed on a first set of the plurality of second bumps and the fourth semiconductor chip is disposed on a second set of the plurality of second bumps; a plurality of conductive posts connecting the first redistribution layer and the second redistribution layer to each other; and a plurality of external connection terminals disposed under the first redistribution layer.
On the other hand, Chang’s second embodiment discloses a plurality of second bumps (Fig. 9, bumps between third chip and second redistribution layer) disposed on the second redistribution layer (Shown), wherein the third semiconductor chip is disposed on a first set of the plurality of second bumps (Leftmost set of bumps) and the fourth semiconductor chip is disposed on a second set of the plurality of second bumps (rightmost set of bumps); a plurality of conductive posts (80) connecting the first redistribution layer and the second redistribution layer to each other (Shown); and a plurality of external connection terminals (94) disposed under the first redistribution layer (Shown). It would have been obvious to one of ordinary skill before the time of effective filing of the invention to modify Chang’s first embodiment according to the teachings of Chang’s second embodiment such that a plurality of second bumps would be disposed on the second redistribution layer, the third semiconductor chip would be disposed on a first set of the plurality of second bumps, and the fourth semiconductor chip would be disposed on a second set of the plurality of second bumps; a plurality of conductive posts would connect the first redistribution layer and the second redistribution layer to each other; and a plurality of external connection terminals would be disposed under the first redistribution layer, in order to improve the mechanical strength of the device during manufacturing by using rigid connection members such as bumps and conductive posts.
Chang still does not disclose a plurality of first bumps disposed on the first redistribution layer, wherein the first circuit board is disposed on a first set of the plurality of first bumps and the second circuit board is disposed on a second set of the plurality of first bumps. Kim ‘993 discloses a plurality of first bumps (Fig. 1B, solder bumps 808) used to bond a circuit board (810) to a redistribution layer (2000). It would have been obvious to one of ordinary skill in the art before the time of effective filing to modify Chang according to the teachings of Kim ‘993 such that a plurality of first bumps would be disposed on the first redistribution layer, wherein the first circuit board is disposed on a first set of the plurality of first bumps and the second circuit board would be disposed on a second set of the plurality of first bumps, in order to mitigate the mechanical strain between the circuit board and the first redistribution layer during mounting, and provide necessary space between the circuit board and the first redistribution layer to prevent electrical contact between their respective conductive layers.
Regarding claim 18, Chang’s first embodiment teaches wherein an electrical signal of the second semiconductor chip is transmitted to the first redistribution layer through the second bonding wires and the second circuit board (shown in Fig. 6). However, Chang’s first embodiment does not disclose an electrical signal of the fourth semiconductor chip being transmitted to the second redistribution layer through the plurality of second bumps.
On the other hand, Chang’s second embodiment discloses an electrical signal of the fourth semiconductor chip being transmitted to the second redistribution layer through the plurality of second bumps (Shown in Fig. 9). It would have been obvious to one of ordinary skill in the art prior to the time of effective filing of the invention to modify Chang’s first embodiment such that an electrical signal of the fourth semiconductor chip would be transmitted to the second redistribution layer through the plurality of second bumps in order to mitigate the mechanical strain between the fourth semiconductor chip and the second redistribution layer by using solder bumps.
Regarding claim 19, neither Chang in view of Kim ‘993 disclose a pitch between the plurality of first bumps being greater than a pitch between the plurality of second bumps. Nonetheless, it would have been obvious to form the pitch of the first bumps within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device or provide any criticality, the claimed device was not patentably distinct from the prior art device (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
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Regarding claim 20, Chang’s first embodiment discloses a first intermediate molding layer (Fig. 6, 31) disposed on the first circuit board and encapsulating the first semiconductor chip and the first bonding wires (Shown); a second intermediate molding layer (32) disposed on the second circuit board and encapsulating the second semiconductor chip and the second bonding wires (Shown); a lower molding layer (Fig. 6, lower portion of 30; see attached figure) disposed on the first redistribution layer (70) and encapsulating the first intermediate molding layer, the second intermediate molding layer (Shown),and an upper molding layer (upper portion of 30) disposed on the second redistribution layer (Shown) and encapsulating the third semiconductor chip (Shown), the fourth semiconductor chip (Shown).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20220399301 A1) in view of Kim '993 (US 20220084993 A1) as applied to claims 1-11, 13, and 15-20 above, and further in view of Kim '683 (US 20200135683 A1).
Regarding claim 12, Chang in view of Kim ‘993 discloses the semiconductor package of claim 11. However, Chang in view of Kim ‘993 does not disclose wherein the lower structure further comprises an adhesive layer disposed between the first semiconductor chip and the circuit board, wherein the adhesive layer is in contact with an upper surface of the circuit board.
On the other hand, Kim ‘683 discloses wherein the lower structure further comprises an adhesive layer (Fig. 4, 223) disposed between the first semiconductor chip (220) and the circuit board (210), wherein the adhesive layer is in contact with an upper surface of the circuit board (Shown in fig. 4). It would have been obvious to one of ordinary skill before the effective time of filing the invention to modify Chang in view of Kim ‘993 according to the teachings of Kim ‘683 such that the semiconductor package of claim 11 would further include an adhesive layer disposed between the first semiconductor chip and the circuit board, wherein the adhesive layer is in contact with an upper surface of the circuit board, in order to improve structural integrity of the package and integrity of the electrical connections between the first semiconductor chip and the circuit board.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20220399301 A1) in view of Kim '993 (US 20220084993 A1) as applied to claims 1-11, 13, and 15-20 above, and further in view of Lee (US 20210065753 A1).
Regarding claim 14, Chang in view of Kim ‘993 discloses the semiconductor package of claim 11. However, Chang in view of Kim ‘993 does not disclose wherein the first semiconductor chip and the second semiconductor chip comprise a graphics double data rate (GDDR) chip.
On the other hand, Lee discloses wherein the first semiconductor chip and the second semiconductor chip comprise a graphics double data rate chip (Fig. 1, para. 36 "the memory chips 141 to 148 may each be… graphic DDR SDRAM"). It would have been obvious to one of ordinary skill in the art before the time of effective filing to modify Chang in view of Kim ‘993 according to the teachings of Lee such that the first and semiconductor chips would comprise a GDDR chip in order to create a GDDR chip with the increased mechanical strength and connection reliability taught by Chang in view of Kim ‘993.
Response to Arguments
Applicant's arguments filed 8/31/2026 have been fully considered but they are not persuasive. Applicant argued that Chang discloses the wire bonding pads 14 and the circuit layer 16 as being part of the same conductive structure 10, and that it would therefore not have been obvious to include first bumps physically separating the circuit layer 16 from the bonding pads 14. Examiner disagrees with Applicant’s arguments. Examiner asserts that, while Chang may refer to circuit layer 16 and bonding pads 14 as part of the same larger structure, it is still within the broadest reasonable interpretation of the claim to map them to components which, on some level, can be viewed as separate. Additionally, the use of solder bumps as a form of electrical connection is extremely well known in the art and widely used for providing mechanical support during the manufacturing process by mitigating mechanical strain between a base and the components being mounted on said base. Furthermore, it is well-established that a determination of obviousness based on teachings from multiple references does not require an actual, physical substitution of elements. In re Mouttet, 686F.3d 1322, 1332, 103 USPQ2d, 122 (Fed. Cir. 2012). See MPEP 2145 III. For the above reasons, Examiner has reopened prosecution on claims 17-20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST.
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/S.J.S./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
