Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6-7, 10-11, 13 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20220399301 A1).
Regarding claim 1, Chang’s first embodiment discloses a semiconductor package (Fig. 6, 1e)
comprising: a first redistribution layer (portion of 13 beneath the upper surface of 162; see attached figure); a first semiconductor chip (20) disposed on the first redistribution layer; a circuit board (portion of 13 comprising wire bonding pads 14) disposed between the first redistribution layer and the first semiconductor chip; a plurality of bonding wires (51) connecting the first semiconductor chip and the circuit board to each other; a second redistribution layer (4) disposed on the first semiconductor chip; a second semiconductor chip (60) disposed on the second redistribution layer (shown). However, Chang’s first embodiment does not disclose a plurality of conductive posts connecting the first redistribution layer and the second redistribution layer to each other.
On the other hand, Chang’s second embodiment discloses a plurality of conductive posts (Fig. 9, 80) connecting the first redistribution layer and the second redistribution layer to each other (Shown in fig. 9). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Chang’s first embodiment according to the teachings of Chang’s second embodiment such that the first and second redistribution layers would be connected by a plurality of conductive posts because of the structural support a conductive post provides in addition to forming electrical connections, especially when compared to bonding wires.
Regarding claim 2, Chang’s second embodiment further discloses further comprising a plurality of external connection terminals (Fig. 9, 94) disposed under the first redistribution layer (Shown), wherein the second semiconductor chip is disposed on the second redistribution layer, in a flip-chip structure. (Shown in accordance with Fig. 1 of instant application).
Regarding claim 6, Chang’s first embodiment further discloses a molding layer (Fig. 6, 31) disposed on the circuit board and encapsulating the first semiconductor chip and the plurality of bonding wires (Shown).
Regarding claim 7, Chang’s second embodiment further discloses a molding layer (Fig. 9, 31) disposed on the first redistribution layer and encapsulating the first semiconductor chip and the plurality of conductive posts (Shown).
Regarding claim 10, Chang’s first embodiment further discloses a molding layer (Fig. 6, 70) disposed on the second redistribution layer and encapsulating the second semiconductor chip (Shown).
Regarding claim 11, Chang’s first embodiment discloses a semiconductor package (Fig. 6, 1e) comprising: a lower structure; an upper structure stacked on the lower structure (see attached figure); wherein the lower structure comprises: a first redistribution layer (portion of 13 beneath the upper surface of 162; see attached figure); a first semiconductor chip (20) disposed on the first redistribution layer; a plurality of bonding wires (51) connecting the first semiconductor chip and the first redistribution layer to each other; wherein the upper structure comprises: a second redistribution layer (4) disposed on the lower structure; a second semiconductor chip (60) disposed on the second redistribution layer. However, Chang’s first embodiment does not disclose a plurality of external connection terminals disposed on the lower structure, and a plurality of conductive posts connecting the first redistribution layer and the upper structure to each other and a plurality of bumps disposed between the second semiconductor chip and the second redistribution layer.
One the other hand, Chang’s second embodiment discloses a plurality of external connection terminals disposed under the lower structure (Fig. 9, 94). It would have been obvious to one of ordinary skill in the art before the effective time of filing of the invention to modify Chang’s first embodiment according to Chang’s second embodiment such that Chang’s first embodiment would further include a plurality of external connection terminals disposed under the lower structure as is extremely common in the art in order to allow the package to integrate into or be in communication with a larger system such as a computer, tablet, or cell phone.
Chang’s second embodiment further discloses a plurality of conductive posts (Fig. 9, 80) connecting the first redistribution layer and the upper structure to each other (Shown in Fig. 9) and a plurality of bumps disposed between the second semiconductor chip and the second redistribution layer (Fig. 9 shows bumps connecting chip 60 to second redistribution layer 4). It would have been obvious to one of ordinary skill in the art before the effective time of filing of the invention to modify Chang’s first embodiment according to Chang’s second embodiment such that Chang’s first embodiment would further include a plurality of conductive posts connecting the first redistribution layer and the upper structure to each other, and a plurality of bumps disposed between the second semiconductor chip and the second redistribution layer, due to the increased mechanical strength and therefore electrical reliability of connections such as pillars and solder bumps, especially when compared to alternatives such as bonding wires.
Regarding claim 13, Chang’s first embodiment further discloses wherein the second semiconductor chip is disposed on the second redistribution layer in a flip-chip structure (Shown in Fig. 6).
Regarding claim 15, Chang’s first embodiment wherein the lower structure further comprises a lower molding layer (Fig. 6, 31) disposed on the first redistribution layer and encapsulating the first semiconductor chip, the plurality of bonding wires, (Shown in fig. 6), and the upper structure further comprises an upper molding layer (70) disposed on the second redistribution layer and encapsulating the second semiconductor chip (Shown in fig. 6). However, Chang’s first embodiment does not disclose the plurality of conductive posts being encapsulated by the lower molding layer.
On the other hand, Chang’s second embodiment discloses a plurality of conductive posts (Fig. 9, 80). It would have been obvious to one of ordinary skill in the art before the effective time of filing of the invention to modify Chang’s first embodiment according to the teachings of Chang’s second embodiment such that the lower molding layer would further encapsulate a plurality of conductive posts due to the increased mechanical strength of using conductive posts as a means of forming electrical connections, and the further increased mechanical strength produced by encapsulating said conductive posts in a molding layer.
Regarding claim 16, Chang’s second embodiment discloses wherein the upper structure further comprises an underfill layer disposed between the second semiconductor chip and the second redistribution layer and encapsulating the plurality of bumps (Fig. 9, portion of 70 disposed between second chip 60 and second redistribution layer 4 and encapsulating the bumps).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20220399301 A1) as applied to claims 1-2, 6-7, 10-11, 13, 15 and 16 above, and further in view of Kim (US 20200135683 A1).
Regarding claim 12, Chang discloses the semiconductor package of claim 11. However, Chang does not disclose wherein the lower structure further comprises an adhesive layer disposed between the first semiconductor chip and the first redistribution layer, wherein the adhesive layer is in contact with an upper surface of the first redistribution layer.
On the other hand, Kim discloses wherein the lower structure further comprises an adhesive layer (Fig. 4, 223) disposed between the first semiconductor chip (220) and the first redistribution layer (210), wherein the adhesive layer is in contact with an upper surface of the first redistribution layer (Shown in fig. 4). It would have been obvious to one of ordinary skill before the effective time of filing the invention to modify Chang according to the teachings of Kim such that the semiconductor package of claim 11 would further include an adhesive layer disposed between the first semiconductor chip and the first redistribution layer, wherein the adhesive layer is in contact with an upper surface of the first redistribution layer, in order to improve structural integrity of the package and integrity of the electrical connections between the first semiconductor chip and the first redistribution layer.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20220399301 A1) as applied to claims 1-2, 6-7, 10-11, 13, 15 and 16 above, and further in view of Lee (US 20210065753 A1).
Regarding claim 14, Chang discloses the semiconductor package of claim 11. However, Chang does not disclose wherein the first semiconductor chip and the second semiconductor chip comprise a graphics double data rate (GDDR) chip.
On the other hand, Lee discloses wherein the first semiconductor chip and the second semiconductor chip comprise a graphics double data rate chip (Fig. 1, para. 36 "the memory chips 141 to 148 may each be… graphic DDR SDRAM"). It would have been obvious to one of ordinary skill in the art before the time of effective filing to modify Chang according to the teachings of Lee such that the first and semiconductor chips would comprise a GDDR chip in order to create a GDDR chip with the increase mechanical strength and connection reliability taught by the first and second embodiments of Chang.
Allowable Subject Matter
Claims 3-5, 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art of record does not disclose the package of claim 1 further comprising a plurality of first bumps disposed between the circuit board and the first redistribution layer, wherein the plurality of bonding wires electrically connect an upper surface of the first semiconductor chip and an upper surface of the circuit board.
For this reason, claims 4-5 would also be allowable if claim 3 were rewritten in independent form.
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 17, the prior art of record does not disclose a semiconductor package comprising: a first redistribution layer; a first semiconductor chip and a second semiconductor chip, spaced apart from each other in a first direction on the first redistribution layer; a first circuit board disposed between the first redistribution layer and the first semiconductor chip; a second circuit board disposed between the first redistribution layer and the second semiconductor chip; first bonding wires connecting the first semiconductor chip and the first circuit board to each other; second bonding wires connecting the second semiconductor chip and the second circuit board to each other; a plurality of first bumps disposed on the first redistribution layer, wherein the first circuit board is disposed on a first set of the plurality of first bumps and the second circuit board is disposed on a second set of the plurality of first bumps; a second redistribution layer disposed on the first semiconductor chip; a third semiconductor chip and a fourth semiconductor chip, spaced apart from each other in the first direction on the second redistribution layer; a plurality of second bumps disposed on the second redistribution layer, wherein the third semiconductor chip is disposed on a first set of the plurality of second bumps and the fourth semiconductor chip is disposed on a second set of the plurality of second bumps; a plurality of conductive posts connecting the first redistribution layer and the second redistribution layer to each other; and a plurality of external connection terminals disposed under the first redistribution layer, wherein the first semiconductor chip is connected to the first redistribution layer through the first bonding wires and the first circuit board, and the third semiconductor chip is attached to the second redistribution layer, in a flip-chip structure. Specifically, the prior art of record does not disclose a plurality of first bumps disposed on the first redistribution layer, wherein the first circuit board is disposed on a first set of the plurality of first bumps and the second circuit board is disposed on a second set of the plurality of first bumps.
For this reason, claims 18-20 are also allowable as dependents of claim 17.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.J.S./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights