Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“Semiconductor Packages with Ridge-Based Electrical Interconnects and Fluidic Channels, and Methods of Forming the Same”
Because the revised title more accurately reflects the claimed invention by identifying the key inventive feature directed to an integrated electrical and microfluidic semiconductor package architecture.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-10, 12-15 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sikka et al. (US 20200294968; in the IDS on 8/11/25).
Regarding claim 1. Fig 2 of Sikka discloses A semiconductor device comprising:
a first substrate (corresponding to 212) comprising:
a first layer (the layer where 218 is formed) comprising a first channel 214 [0037];
a first via 218 [0037] extending through the first layer (top surface) to a first surface of a first ridge (the ridges adjacent channels 214) of the first channel;
a second layer 216 coupled to the first layer, wherein the second layer is a first outer layer of the first substrate (Fig 2); and
a first line (corresponding to the laterally extending conductive feature shown within the second layer 216 in Fig. 2) coupled to the first via and extending along the first ridge of the first channel and embedded in the second layer (the first line being coupled to the first via through electrically conductive connection 220, extending along the first ridge of the first channel, and embedded in the second layer 216).
Regarding claim 2. Sikka discloses The semiconductor device of claim 1, wherein the first line is located between the first layer and the second layer (the first line is embedded within the second layer 216 and is positioned adjacent to the interface between the first layer and the second layer. Accordingly, the first line is located between the first layer and the second layer).
Regarding claim 4. Sikka discloses The semiconductor device of claim 1, wherein the first line is connected to a bonding pad (Fig 2, [0031], [0037]; e,g. 204).
Regarding claim 5. Sikka discloses The semiconductor device of claim 4, wherein the bonding pad is connected to at least one of a second via, a pad, or an other bonding pad located on a second substrate (Fig 2: corresponding to 112).
Regarding claim 6. Sikka discloses The semiconductor device of claim 1, further comprising:
a second substrate (Fig 2: corresponding to 112) comprising:
a third layer (the layer where 118 is formed) comprising a second channel 114 [0025];
a second via 118 [0032] extending through the third layer to a second surface (top surface) of a second ridge (the ridges adjacent channels 114) of the second channel;
a fourth layer 116 coupled to the third layer, wherein the fourth layer is a second outer layer of the second substrate (Fig 2); and
a connector (corresponding to the laterally extending conductive feature shown within the second layer 116 in Fig. 2) connected to the second via and the first line and embedded in the fourth layer (Fig 2).
Regarding claim 7. Sikka discloses The semiconductor device of claim 6, wherein the connector is a second line extending across the second ridge of the second channel (Fig 2).
Regarding claim 8. Sikka discloses The semiconductor device of claim 7, wherein the first line is connected to the second line by a bonding pad (Fig 2, [0031], [0037]; e,g. 204. They are electrically connected via 204).
Regarding claim 9. Sikka discloses The semiconductor device of claim 6, wherein the connector is a pad (Fig 2, [0031], [0037]; e,g. 204).
Regarding claim 10. Sikka discloses The semiconductor device of claim 6, wherein the second ridge of the second channel is offset from the first ridge of the first channel (Fig 2: the second channel 114 is not vertically aligned with the first channel 214, but is laterally displaced such that the second channel is vertically aligned beneath the first via 118).
Regarding claim 12. Sikka discloses The semiconductor device of claim 6, wherein the first via is located over the second channel (Fig 2: the first via 218 is vertically aligned over the second channel 114 in the stacked semiconductor device).
Regarding claim 13. Sikka discloses The semiconductor device of claim 6, wherein the second substrate comprises one or more inlet or outlet ports configured to receive a fluid, wherein the fluid is received in the first channel and the second channel ([0030]: the second substrate comprises one or more inlet and/or outlet ports configured to receive a fluid. Specifically, one or more inlet holes and one or more outlet holes are formed through the cap or through the chip, the inlet holes being configured to receive coolant fluid, which flows through the cooling channels and exits through the outlet holes).
Regarding claim 14. Fig 2 of Sikka discloses A semiconductor device comprising:
a first substrate (corresponding to 212) comprising:
a first layer (the layer where 218 is formed) comprising a first channel 214;
a first via 218 extending to a first surface (top surface) of the first layer,
wherein the first surface is a surface of a first ridge (the ridges adjacent channels 214) of the first channel;
a second layer 216 coupled to the first layer, wherein the second layer is a first outer layer of the first substrate (Fig 2); and
a first line (corresponding to the laterally extending conductive feature shown within the second layer 216 in Fig 2) connected to the first via and extending across the first ridge of the first channel (Fig 2); and
a second substrate (corresponding to 112) comprising:
a third layer (the layer where 118 is formed) comprising a second channel 114;
a second via 118 extending to a second surface of the third layer, wherein the second surface is a surface (top surface) of a second ridge (the ridges adjacent channels 114) of the second channel;
a fourth layer 116 coupled to the third layer, wherein the fourth layer is a second outer layer of the second substrate (Fig 2); and
a connector (Fig 2: the 120, the middle layer and 122 within 116) coupled to the second via and the first line (Fig 2: they are electrically coupled).
Regarding claim 15. Sikka discloses The semiconductor device of claim 14, wherein the connector comprises a second line (corresponding to the laterally extending conductive feature shown within the second layer 116 in Fig 2) extending across the second ridge of the second channel (Fig 2).
Regarding claim 17. Fig 2 and Fig 8 (flowchart of forming method) of Sikka discloses A method of manufacturing a semiconductor device, the method comprising:
forming a first substrate (corresponding to 212) comprising:
forming a first layer (the layer where 218 is formed);
forming a first channel 214 in the first layer;
forming a first via 218 in the first layer extending to a first ridge (the ridges adjacent channels 214) of the first channel;
forming a first line (corresponding to the laterally extending conductive feature shown within the second layer 216 in Fig 2) extending along the first ridge of the first channel and connected to the first via (Fig 2); and
forming a second layer 216 on the first ridge of the first channel and surrounding the first line (Fig 2: the first line is within 216).
Regarding claim 18. Sikka discloses The method of claim 17, further comprising:
forming a second substrate (corresponding to 112) comprising:
forming a third layer (the layer where 118 is formed);
forming a second channel 114 in the third layer (Fig 2);
forming a second via 118 in the third layer extending to a second ridge (the ridges adjacent channels 114) of the second channel;
forming a connector (Fig 2: the connector including 120, the middle layer, and 122) coupled to the third layer and connected to the second via and the first line (they are electrically connected); and
forming a fourth layer 116 on the second ridge of the second channel and surrounding the connector (Fig 2: because the connector is within 116).
Regarding claim 19. Sikka discloses The method of claim 18, wherein the connector comprises a second line (corresponding to the laterally extending conductive feature shown within the second layer 116 in Fig 2) extending along the second ridge and connected to the first line (Fig 2).
Regarding claim 20. Sikka discloses The method of claim 18, wherein the second layer is formed in one or more first selected locations based on one or more first locations where the first line is formed, wherein the fourth layer is formed in one or more second selected locations based on one or more second locations where the connector is formed (Fig 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Sikka et al. (US 20200294968; in the IDS on 8/11/25) in view of Koontz et al. (US 20140264759).
Regarding claim 3. Sikka discloses The semiconductor device of claim 1. Sikka does not expressly disclose that the second layer is a dielectric layer.
However, Koontz teaches forming an oxide layer on a semiconductor wafer surface. Specifically, Fig. 1A illustrates an oxide layer formed on the second surface 128 of wafer 108, and paragraph [0027] discloses that an oxide layer is formed on the second surface 128 of the wafer, wherein the oxide layer comprises silicon dioxide formed on the silicon wafer surface. Paragraph [0027] further explains that silicon dioxide layers are formed on silicon surfaces using semiconductor processing techniques. Since silicon dioxide is a dielectric material, Koontz teaches that the second layer is a dielectric layer. Paragraphs [0028]-[0029] further disclose bonding the oxide surfaces of wafers 108 and 112 to form the wafer assembly shown in Fig. 1B.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the second layer of Sikka as a dielectric layer, as taught by Koontz, in order to electrically insulate conductive features while providing a bonded sealing layer for the fluid channels.
Claims 11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Sikka et al. (US 20200294968; in the IDS on 8/11/25).
Regarding claim 11. Sikka discloses The semiconductor device of claim 6. But Sikka does not expressly disclose in the embodiment of Fig. 2 that the second ridge of the second channel is about perpendicular to the first ridge of the first channel.
However, Sikka teaches an alternative embodiment in Fig. 7C in which the stacked chips are rotated approximately 90 degrees relative to one another. Specifically, paragraph [0052] discloses that chips 128 and 112 are stacked with orientations that are rotated 90 degrees relative to one another, such that the microfluidic tubes (coolant channels) of chip 128 are positioned at 90-degree angles relative to the microfluidic tubes of chip 112. As a result, the ridges of the coolant channels of the upper chip are about perpendicular to the ridges of the coolant channels of the lower chip.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the embodiment of Fig. 2 by orienting the second substrate relative to the first substrate as taught by the embodiment of Fig. 7C, thereby providing the second ridge of the second channel about perpendicular to the first ridge of the first channel. Sikka expressly teaches that the chips may be rotated 90 degrees to facilitate providing space for the microfluidic tubes located between stacked chips [0052]. Such a modification merely substitutes one disclosed orientation of stacked chips for another disclosed orientation taught by the same reference while achieving the known benefit taught by Sikka.
Regarding claim 16. Sikka discloses The semiconductor device of claim 14. But Sikka does not expressly disclose wherein a ratio of a thickness of the second layer to a thickness of the first line is between about 1:1 to about 30:1.
However, because the first line is completely embedded within the second layer, the relative thicknesses of the second layer and the first line are a matter of design choice and represent a result-effective variable that would have been optimized by one of ordinary skill in the art to provide adequate electrical insulation, structural integrity, and manufacturability. Selecting a ratio of the thickness of the second layer to the thickness of the first line within the claimed range of about 1:1 to about 30:1 would have been an obvious matter of routine optimization. Furthermore, the instant specification does not disclose that the claimed range is critical or that it achieves any unexpected results relative to other thickness ratios. Accordingly, the claimed range would have been obvious to one of ordinary skill in the art.
Conclusion
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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