DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application filed on 04/29/2024.
Currently claims 1-20 are pending in the application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/17/2024 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 7, and 9 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by US 2019/0348494 A1 (Leng).
Regarding claim 1, Leng discloses, an integrated circuit (Fig. 3; Figs. 4A-4I; [0024]-[0037]) comprising:
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a first dielectric layer over a semiconductor substrate (dielectric structure including field oxide 202, trench etch stop layer 204, and oxide region 230 (oxide layers 206/226) formed over a previously processed semiconductor substrate; Figs. 4A-4B, 4G; [0006], [0025]-[0027], [0033]);
first and second metal terminals extending from a top surface of the first dielectric layer toward the semiconductor substrate (metal TFR head/contact structures 104, formed by filling M1 trenches 234 that are etched from the top surface of oxide region 230 downward toward the substrate, stopping on TFR element 216 and extending down to field oxide 202 laterally outside the TFR element; Fig. 3; Figs. 4H-4I; [0024], [0034], [0036]);
a resistive layer extending between and electrically connected to the first and second metal terminals (TFR film/element 106/216 extending laterally between, and contacted at opposing sides by, head/contact structures 104; Fig. 3; [0024], [0028], [0034], [0036]); and
a second dielectric layer over and in direct contact with the resistive layer (dielectric cap layer 220, e.g., SiN, deposited directly on TFR film 216 to protect the TFR film; shown in Fig. 3 as upper dielectric layer 110 in direct contact with TFR film 106; Fig. 4E; [0024], [0030]).
Regarding claim 2, Leng further discloses, wherein the second dielectric layer is thicker than the resistive layer (dielectric cap layer 220 may comprise a SiN layer with a thickness of about 750 Å (e.g., 600 Å-900 Å; [0031]), whereas TFR layer 216 has a thickness of about 500 Å (e.g., 400 Å-600 Å; [0029]); further, the overlying dielectric on the resistive layer, including cap layer 220 and additional trench oxide 226, has a combined thickness (Toxide) of about 4K Å; [0028], [0030], [0033]).
Regarding claim 7, Leng further discloses, wherein the first and second metal terminals are in a horizontal metal interconnect routing layer (TFR head/contact structures 104 are defined by the “metal 1” (M1) interconnect layer and are formed in M1 trenches 234 as part of a typical CMOS M1 creation process; [0021], [0034], [0036]-[0037]).
Regarding claim 9, Leng further discloses, wherein the first and second metal terminals comprise copper (M1 trenches 234 are filled with copper, including a copper diffusion barrier/seed layer 240 followed by copper plating, anneal and CMP; Fig. 4I; [0037]).
Claims 10, 13 and 15 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by US 2019/0348494 A1 (Leng).
Regarding claim 10, Leng discloses, a method (method of forming an IC structure including a TFR module; Figs. 4A-4I; [0025]-[0037]) comprising:
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forming a first dielectric layer over a semiconductor substrate (forming trench etch stop layer 204 and oxide layers 206/226 (oxide region 230) over field oxide 202 of a previously processed semiconductor substrate; Figs. 4A-4B, 4G; [0025]-[0027], [0033]);
forming first and second metal terminals extending from a top surface of the first dielectric layer toward the semiconductor substrate (242; TFR heads/contacts going both upward and downward from 204; Figs. 4H-4I; [0034], [0037]);
forming a resistive layer (TFR layer 216) extending between and electrically connected to the first and second metal terminals (depositing TFR layer 216, e.g., SiCr, into TFR trench 212 such that the resulting TFR element 216 extends between and is contacted by the head/contact structures; Fig. 4D; [0028], [0034], [0036]); and
forming a second dielectric layer over and in direct contact with the resistive layer (depositing dielectric cap layer 220, e.g., SiN, directly on TFR film 216; Fig. 4E; [0030]).
Regarding claim 13, Leng further discloses, the method of claim 10, wherein the first and second metal terminals are formed in a horizontal metal interconnect routing layer (head/contact structures are defined by the “metal 1” (M1) layer and formed in M1 trenches 234 as part of a typical CMOS M1 creation process; [0021], [0034], [0036]-[0037]).
Regarding claim 15, Leng further discloses, the method of claim 10, wherein the resistive layer is selected from the group consisting of silicon chromium (SiCr) and nickel chromium (NiCr) (TFR layer 216 may comprise a SiCr layer; in other embodiments TFR layer may comprise SiCCr, TaN, NiCr, AlNiCr, TiNiCr; [0028] –[0029]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0348494 A1 (Leng) in view of US 2019/0109186 A1 (Leng2).
Regarding claim 3, Leng fails to teach explicitly, an interconnect metal structure extending through the second dielectric layer and conductively connecting to the first or second metal terminal (Leng ends its disclosure at the M1 level and does not show interconnect structures formed through the dielectric overlying the TFR module to reach the head/contact structures 104).
However, in analogous art, Leng2 discloses, via-type contacts 260 formed by patterning and etching via openings through overlying dielectric layers (PSG layer 210E and USG cap oxide layer 210F) located over the TFR film, and filling the via openings with a conductive material to conductively connect to the underlying TFR head structures 204 (Fig. 4K; [0027]-[0028]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Leng and Leng2 before him/her, to modify the IC of Leng by forming an interconnect metal structure through the dielectric overlying the TFR module to conductively connect to the metal terminals, as taught by Leng2, in order to connect the TFR module to subsequent interconnect/metallization levels (Cu or Al) of the IC (Leng2; [0007], [0029]). Both references are directed to damascene TFR integration, and the combination is merely the application of a known technique (via formation through an overlying dielectric) to a known device ready for improvement, yielding the predictable result of a vertically connected TFR module. Absent this teaching in Leng, a person with ordinary skill in the art would be motivated to reach out to Leng2 while forming an integrated circuit of Leng.
Regarding claim 4, the combination of Leng and Leng2 further discloses, wherein the interconnect metal structure is a via (via-type contacts 260 formed in via openings; Leng2; Fig. 4K; [0028]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0348494 A1 (Leng) in view of US 2021/0273037 A1 (Fest).
Regarding claim 8, Leng fails to teach explicitly, wherein the first and second metal terminals are tungsten contacts (the head/contact structures 104 of Leng are copper damascene structures; [0036]).
However, in analogous art, Fest discloses, an IC structure in which tungsten contacts (tungsten vias 114) serve as the conductive terminal structures, extending from a top surface of a dielectric (bulk insulation region 120) toward the semiconductor substrate (to transistor structure 112 formed over substrate 113), the tungsten contacts being formed and planarized (W CMP) before formation of the TFR film so that the TFR film can subsequently be formed and annealed at a temperature of 500° C. or more without damaging interconnect metal ([0006], [0052]-[0055]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Leng and Fest before him/her, to substitute tungsten contacts, as taught by Fest, for the copper terminal structures of Leng, since (i) this is a simple substitution of one known TFR terminal/contact metallurgy for another yielding predictable results; and (ii) tungsten terminals withstand the high-temperature TFR anneal (about 500° C.) that Leng itself identifies as desirable for achieving 0 ppm or near 0 ppm TCR (Leng; [0007], [0029]; Fest; [0006]). Absent this teaching in Leng, a person with ordinary skill in the art would be motivated to reach out to Fest while forming an integrated circuit of Leng.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0348494 A1 (Leng) as applied to claim 10 and further in view of US 2019/0109186 A1 (Leng2).
Regarding claim 14, Leng fails to teach explicitly, the method of claim 10, wherein the first dielectric layer is a pre-metal dielectric (PMD) layer and the first and second metal terminals are formed as tungsten contacts in the PMD layer and coupled to polysilicon interconnect traces.
However, Leng2 discloses, the method of claim 10, wherein the first dielectric layer is a pre-metal dielectric (PMD) layer and the first and second metal terminals are formed as tungsten contacts in the PMD layer and coupled to polysilicon interconnect traces (the TFR module of Leng2 is formed in PMD (poly-metal dielectric, between poly and metal 1) [0009]; via-type contacts 260 are formed within the PMD dielectric stack (PSG layer 210E/USG layer 210F) by etching via openings and filling them with tungsten (W), the contacts 260 being connected to the TFR heads 204 and thereby coupled to the polysilicon structures 208 through silicide layers 206; Figs. 4A, 4J-4K; [0017], [0023]-[0028]). Constructing the TFR module in the PMD before metallization allows the TFR to be annealed at high temperature (about 500°C) without harm to the interconnect metals (Cu or Al) ([0007], [0009]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Leng and Leng2 before him/her, to modify the fabrication method of Leng to form the metal terminal structures prior to depositing the resistive film, as taught by Leng2, since both references address damascene TFR integration in semiconductor processes, and Leng2 teaches that forming the terminal/head structures before depositing the TFR film allows the TFR film to land on and directly bridge the pre-formed heads, providing reliable electrical contact while reducing added mask layers (Leng2; [0008]-[0009], [0030]). This constitutes a simple substitution of one known fabrication sequence (TFR-film-first) for another (terminals-first) yielding the predictable result of a TFR electrically connected to pre-formed metal terminal structures; moreover, the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results (In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); MPEP 2144.04(IV)(C)). Absent this teaching in Leng, a person with ordinary skill in the art would be motivated to reach out to Leng2 while forming an integrated circuit of Leng.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0109186 A1 (Leng2) and further in view of US 2021/0273037 A1 (Fest).
Regarding claim 16, Leng2 discloses, an integrated circuit (IC) (Fig. 3; Figs. 4A-4K; [0016]-[0028]) comprising:
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a pre-metal dielectric (PMD) layer over a semiconductor substrate (PMD dielectric region including layers 210A-210F formed over the substrate, the TFR module being formed in PMD (poly-metal dielectric, between poly and metal 1); [0009], [0017]-[0020], [0027]);
first and second polysilicon traces between the PMD layer and the semiconductor substrate (poly structures 208 disposed on field oxide 210A beneath the PMD dielectric; Fig. 4A; [0017]);
first and second metal contacts in the PMD layer, each extending vertically from a corresponding polysilicon trace to a top surface of the PMD layer (tungsten via-type contacts 260, each extending vertically from silicide layer 206 on a corresponding poly structure 208 to the top surface of the PMD dielectric stack; Fig. 4K; [0023]-[0028]);
a resistive layer electrically connected to the first and second metal contacts (TFR film 240/250 bridging the TFR heads 204 to which contacts 260 are connected; [0022]-[0023], [0028]); and
a second dielectric layer over the resistive layer (cap oxide 210D, PSG layer 210E and USG cap oxide layer 210F formed over the TFR film; [0025], [0027]).
But Leng2 fails to teach explicitly, the resistive layer being over the PMD layer (in Leng2, TFR film 240 is deposited into a trench 232/234 formed within the PMD dielectric and lands directly on the silicide TFR heads, rather than being disposed over the top surface of the PMD layer and electrically connected to the metal contacts at that surface; [0022]-[0023], [0026]).
However, in analogous art, Fest discloses, an IC wherein a TFR element 134A (e.g., SiCr, SiCCr) is formed over the top surface of a pre-metal bulk insulation region 120 (on a dielectric etch stop layer 132 formed over PMD cap layer 120C), after tungsten vias 114 have been formed extending vertically through region 120 to its top surface and planarized by W CMP ([0052]-[0062]); the TFR element is electrically connected to the tungsten contacts (metal interconnect element 180C conductively connects a first side of TFR element 134A with tungsten via 114A; [0022], [0063], [0065]); and a dielectric layer (TFR oxide cap 136A) is formed over the TFR element ([0056]-[0057], [0061]); thus teaching that a TFR element can be placed over the PMD top surface and electrically connected to tungsten contact structures accessible at that surface.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Leng2 and Fest before him/her, to modify the integrated circuit of Leng2 to position the TFR film over the top surface of the PMD layer and electrically connect it to the tungsten contacts accessible at the PMD top surface, as taught by Fest, since doing so (i) allows the TFR to be formed and annealed at high temperature (500°C. or more) after contact formation but before the first metal/interconnect layer, avoiding damage to aluminum or copper interconnect (Fest; [0006]; Leng2 expresses the same need at [0007]); (ii) eliminates the TFR trench etch into the PMD and its associated masking steps, reducing process complexity; and (iii) maintains full compatibility with Leng2’s polysilicon-trace and tungsten-contact structure. The tungsten contacts of Leng2 already terminate at the top surface of the PMD dielectric stack and are directly accessible to a TFR film formed thereover, providing a reasonable expectation of success. Absent this teaching in Leng2, a person with ordinary skill in the art would be motivated to reach out to Fest while forming an integrated circuit of Leng2.
Regarding claim 17, the combination of Leng2 and Fest further discloses, a copper interconnect formed through the second dielectric layer (Fest: Metal 1 layer 160 may comprise copper and extends into TFR contact openings 156 formed through the TFR oxide cap over the TFR element; [0061] - [0064]; see also Leng2, teaching suitability of the TFR for Cu interconnects; [0008], [0029]). The motivation to combine is the same as set forth for claim 16.
Regarding claim 18, the combination of Leng2 and Fest further discloses, an aluminum interconnect formed through the second dielectric layer (Fest: in the illustrated embodiment, Metal 1 layer 160 comprises aluminum, extends into TFR contact openings 156 formed through the TFR oxide cap, and is etched to define aluminum interconnect elements; Fig. 1K; 180A-180D; [0063], [0065]; see also Leng2, teaching suitability of the TFR for Al interconnects; [0008], [0029]). The motivation to combine is the same as set forth for claim 16.
Regarding claim 19, the combination of Leng2 and Fest further discloses, wherein the first and second metal contacts are tungsten contacts (Leng2: via-type contacts 260 filled with tungsten (W); [0029]; Fest: tungsten vias 114; [0052]). The motivation to combine is the same as set forth for claim 16.
Regarding claim 20, the combination of Leng2 and Fest further discloses, wherein the resistive layer is selected from the group consisting of silicon chromium (SiCr) and nickel chromium (NiCr) (Leng2: TFR layer 240 may comprise a SiCr layer; in other embodiments, SiCCr, TaN, NiCr, AlNiCr, TiNiCr; [0023]; Fest: TFR film layer 134 may comprise SiCr, among others; [0017], [0054]). The motivation to combine is the same as set forth for claim 16.
Allowable Subject Matter
Claims 5, 6, 11, and 12 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claims 5 and 6, the closest prior art, Leng (US 2019/0348494 A1), Leng2 (US 2019/0109186 A1), Fest (US 2021/0273037 A1), and Schrum et al. (US 2007/0069334 A1), alone or in combination, fails to disclose, “the IC of claim 1, wherein the resistive layer conformally covers a sidewall of a metal diffusion barrier layer on the first metal terminal” (claim 5), and “wherein the metal diffusion barrier layer comprises cobalt or tungsten” (claim 6), in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, in Leng the copper diffusion barrier layer (Ta/TaN layer 240) is deposited into the head/contact trenches after the TFR element is formed, such that the barrier overlies the TFR element rather than the resistive layer conformally covering a sidewall of a barrier layer disposed on the terminal ([0036]). Schrum teaches only a blanket titanium-tungsten (TiW) diffusion barrier deposited over the NiCr resistor. None of the references discloses or suggests a resistive layer that conformally covers a sidewall of a cobalt or tungsten metal diffusion barrier layer on the metal terminal. The aforementioned limitation is material to the inventive concept of the application at hand to provide direct, barrier-protected contact between the resistive layer and terminal metal (e.g., copper routing features) without separate resistor head structures, while protecting the terminal metal during resistor formation (see specification at [0033]-[0038]).
Regarding claims 11 and 12, claim 11 depends from claim 10 and recites that the resistive layer is conformally formed to cover a sidewall of a metal diffusion barrier layer on the first metal terminal; claim 12 further specifies that the metal diffusion barrier layer is formed by area selective metal deposition and comprises cobalt or tungsten.
The prior art of record does not disclose or suggest area-selective deposition of a cobalt or tungsten diffusion barrier layer on the first metal terminal followed by conformal coverage of a sidewall of that barrier layer by the thin film resistive layer. Area-selective metal deposition of the barrier — as distinguished from non-selective blanket deposition such as the blanket TiW barrier of Schrum or the blanket Ta/TaN barrier of Leng — is a method feature not taught or suggested by any reference of record. Claims 11 and 12 are therefore allowable over the prior art of record for reasons analogous to those given for claims 5 and 6.
The examiner notes that applicant may expedite prosecution by amending independent claim 1 to incorporate the limitations of claims 5 and 6 (a diffusion barrier layer comprising cobalt or tungsten on the first metal terminal, with the resistive layer conformally covering a sidewall of the barrier layer), and by amending independent claim 10 to incorporate the limitations of claims 11 and 12 (area-selective deposition of the cobalt or tungsten diffusion barrier layer, conformally covered by the resistive layer). Such amendments would place the independent claims in condition for allowance.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2007/0069334 A1 (Schrum) – Thin film resistors integrated at two different metal interconnect levels of a single die. A NiCr thin film resistor (3) is formed with a blanket titanium-tungsten (TiW) diffusion barrier layer (4) deposited over the resistor to serve as a diffusion barrier between the NiCr resistor and the subsequently deposited Metal 1 (aluminum) conductors (5A-5C). This reference confirms that blanket (non-selective) diffusion barriers in TFR contexts are known in the art, in contrast to the area-selective barrier deposition and conformal resistive-layer coverage recited in claims 5, 6, 11, and 12.
US 2015/0349045 A1 (Wang) - An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a substrate and a polysilicon resistor. The polysilicon resistor is disposed on the substrate. The polysilicon resistor has at least one positive TCR portion and at least one negative TCR portion. The positive TCR portion is adjacent to the negative TCR portion, and the positive TCR portion is in direct contact with the negative TCR portion.
US 2009/0023263 A1 (Phan) - A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material layer on a semiconductor substrate. The process also includes depositing an insulating layer on the resistive material layer, and performing a first dry etch process on the insulating layer to form an insulative body. The process further includes performing a second dry etch process on the resistive material layer to form a resistive body. The resistive body and the insulative body have substantially identical perimeters.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
07/15/2026
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