Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-16 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rajan et al (Pub. No.: US 2018/0285013).
Regarding independent claims 1 and 14, Rajan discloses a memory device (Fig.1A: Memory Module 100) comprising:
a command interface (Fig.1A: RCD 115) having a first command port (Fig.1A: CAA) and a second command port (Fig.1A: CAB);
a command decoder (Fig.1A: [0070] Address-buffer component 115 includes a number of circuits. Such circuits may include a command decoder) to decode a first command received on both the first command port (Fig.1A: CAA) and the second command port (Fig.1A: CAB) in a wide-data mode (abstract: wide-data mode) and to decode a second command received on one of the first command port (Fig.1A: CAA) and the second command port (Fig.1A: CAB) in a narrow-data mode (abstract: narrow-data mode) (abstract: memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.);
a data interface (Fig.1A: Module Data Connections 114) having a first data port (Fig.1A: DQu) to communicate first data signals and a second data port (Fig.1A: DQv) to communicate second data signals (Fig.1A and [0032]: Each nibble-wide primary data port DQu and DQv is accompanied by two lines that convey a respective one of complementary strobe signals DQSup± and DQSvp±. ); and
a data switch coupled to the data interface, the data switch communicating the first data signals concurrently with the second data signals over both the first data port (Fig.1A: DQu) and the second data port (Fig.1A: DQv) in the wide-data mode (abstract: wide-data mode) and communicating the first data signals in succession with the second data signals over one of the first data port (Fig.1A: DQu) and the second data port (Fig.1A: DQv) in the narrow-data mode (abstract: narrow-data mode) (abstract: narrow-data mode) (abstract: memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the
Regarding claim 2, Rajan teaches a first memory connected to the data switch to store the first data signals and a second memory connected to the data switch to store the second data signals (Fig.1A and [0026]: A memory controller (not shown) directs command, address, and control signals on primary ports DCA and DCNTL to control the flow of data to and from module 100 via eighteen groups of data links DQu and DQv to module data connections 114. Address-buffer component 115, alternatively called a “Registering Clock Driver” (RCD), selectively interprets and retransmits the control signals on a module control interface 116 (signals DCA and DCNTL) from module control connections 118 and communicates appropriate command, address, control, and clock signals to a first set of memory components 105 via a first memory-component control interface 120A and to a second set of memory components via a second memory-component control interface 120B. Addresses associated with the commands on primary port DCA identify target collections of memory cells (not shown) in components 105, and chip-select signals on primary port DCNTL and associated with the commands allow address-buffer component 115 to select individual integrated-circuit DRAM dies, or “chips,” for both access and power-state management.).
Regarding claim 3, Rajan teaches wherein the first memory comprises a first array of memory banks and the second memory comprises a second array of memory banks (Fig.1A: DRAMs 105 comprises array of memory backs).
Regarding claim 4, Rajan teaches a command-training circuit selectively coupled to one of the first data port and the second data port via the data switch, the command-training circuit to convey training data over the one of the first data port and the second data port in the narrow-data mode (abstract and [0070]: Address-buffer component 115 includes a number of circuits that are omitted here. Such circuits may include a phase-locked loop, training and built-in self-test (BIST) logic, a command buffer, and a command decoder).
Regarding claim 5, Rajan teaches a command switch coupled to the first command port to direct the training data from the first command port to the command-training circuit (abstract and [0070]: Address-buffer component 115 includes a number of circuits that are omitted here. Such circuits may include a phase-locked loop, training and built-in self-test (BIST) logic, a command buffer, and a command decoder).
Regarding claims 6 and 19, Rajan teaches wherein the first command port and the second command port include equal numbers of command pads (Fig.1A: CAA and CAB are evenly connected to the DRAMs).
Regarding claim 7, Rajan teaches wherein the data switch communicates the first data signals and the second data signals at a faster data rate in the wide-data mode relative to the narrow-data mode ([0024]: FIG. 1A depicts a memory module 100 that can be configured to support different data widths. In this example, module 100 supports a wide-data mode in which module 100 communicates nine eight-bit data bytes (72 data bits) in parallel, and is compatible with what is conventionally termed a “DDR4 LRDIMM chipset.” DDR4 (for “double-data-rate, version 4”) is a type of dynamic, random-access memory (DRAM) die, and LRDIMM (for “load-reduced, dual inline memory module”) is a type of memory module that employs a separate system of buffers to facilitate communication with the memory dies. This backward compatibility is important because it allows module 100 to support an enormous and growing range of memory systems. Module 100 additionally supports a narrow-data mode in which module 100 communicates nine four-bit data nibbles (36 data bits) in parallel, and that can be used in support of improved signaling integrity, higher signaling rates, and increased system memory capacity. Thus, it can be faster data rate in the wide-data mode relative to the narrow-data mode).
Regarding claim 8, Rajan teaches wherein the faster data rate is double the data rate in the narrow-data mode ([0024]: Module 100 additionally supports a narrow-data mode in which module 100 communicates nine four-bit data nibbles (36 data bits) in parallel, and that can be used in support of improved signaling integrity, higher signaling rates, and increased system memory capacity).
Regarding claim 15, Rajan teaches wherein the command interface issues the wide command over a number of clock cycles and issues the narrow command over more than the number of clock cycles (Fig.5 and [0071]-[0075]).
Regarding claim 16, (Original) The memory controller of claim 15, wherein the command interface issues the narrow command over twice the number of clock cycles (Fig.5 and [0071]-[0075]).
Allowable Subject Matter
Claims 17 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 17 identifies the distinct features “a first variable- delay read circuit between the control logic and the first data port and a second variable-delay read circuit between the control logic and the second data port ", which are not taught or suggested by the prior art of records.
Claim 18 identifies the distinct features “a first variable- delay write circuit between the control logic and the first data port and a second variable-delay write circuit between the control logic and the second data port", which are not taught or suggested by the prior art of records.
Claims 17 and 18 would be allowable over the prior art of record because the claimed features as mentioned above in combination with other claimed features are not recited or suggested by the prior art of records.
Response to Arguments
Applicant’s arguments filed on 12/31/2025 have been fully considered but they are not persuasive.
1st Point of Argument
Regarding Applicant’s remarks on page 4, the applicants argue that Rajan does not disclose a command decoder that decodes commands received on both first and second command ports
In response, under the broadest reasonable interpretation (BRI) of the claim language, the recitation of “a command decoder … to decode …” merely describes an intended use or capability of the recited structure, and does not require that the command decoder actually perform the decoding in the specific manner asserted by Applicant. The claim does not positively require that the command decoder be shown to actually decode commands received from both ports in operation, but rather that it is configured for such functionality. Thus, this argument is not persuasive.
2nd Point of Argument
Regarding Applicant’s remarks on page 4, the applicants argue that Rajan's ports labeled CAA and CAB do not receive commands as inputs to the command decoder.
In response, under the broadest reasonable interpretation (BRI) of the claim language, the claim limitation “a command decoder to decode a first command received on both the first command port and the second command port” does not require that the first command be received as an input directly to the command decoder. The claim merely recites a command decoder configured to decode a first command, without specifying that the first command must be input to the decoder from the recited ports. Thus, this argument is not persuasive.
3rd Point of Argument
Regarding Applicant’s remarks on page 4, the applicants argue that there are no first and second command ports to receive the same command in the manner claimed
In response, under the broadest reasonable interpretation (BRI) of the claim language, the claim requires that a first command be received on both ports, but does not require that the command be independently or directly received at each port. In Rajan, a command received via the primary command/address bus is distributed and conveyed via multiple signal paths, including CAA and CAB, to different memory component interfaces (Fig.1A, Fig.1B and [0034]). Thus, this argument is not persuasive.
In view of the foregoing, the rejection under 35 USC § 102 is maintained.
However, if Applicant amends the claims to explicitly recite that both command ports receive the same command as an input, such as by requiring simultaneous or direct receipt at both command ports, or to further clarify that the command decoder actually performs decoding of the first command received on both command ports, the applied prior art does not teach or suggest such limitations. Accordingly, upon such amendment, the rejection under 35 USC § 102 would be withdrawn.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Giovannini et al. (PATENT. No.: US 10,789,185) “Memory Modules And Systems With Variable-width Data Ranks And Configurable Data-rank Timing”
Considered for teachings related to a memory system that supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules.
Does not disclose or suggest a command interface having a first command port and a second command port; a command decoder to decode a first command received on both the first command port and the second command port in a wide-data mode and to decode a second command received on one of the first command port and the second command port in a narrow-data mode;a data interface having a first data port to communicate first data signals and a second data port to communicate second data signals; anda data switch coupled to the data interface, the data switch communicating the first data signals concurrently with the second data signals over both the first data port and the second data port in the wide-data mode and communicating the first data signals in succession with the second data signals over one of the first data port and the second data port in the narrow-data mode.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov. The examiner can normally be reached on M-F 8:00am to 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535. Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100.
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/YONG J CHOE/Primary Examiner, Art Unit 2135
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