Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/ Restrictions
Applicant's election of group I without traverse: claims 11-20, in the “Response to Election / Restriction Filed - 08/03/2026”, withdrawal of non-elected claim(s) 1-10 is/are acknowledged. This office action considers claims 1-20, in “Claims - 04/29/2024”, pending for prosecution, of which claim(s) 1-10 is/are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 11-12, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saito et al. (US 20120286231 A1 – hereinafter Saito).
Regarding Claim 11, Saito teaches a method of forming an integrated circuit (see the entire document; Figs. 1-2; specifically, ([0038] - [0050]), and as cited below), comprising:
forming a resistive layer (9 – Fig. 1 - [0038]) over a semiconductor substrate (silicon substrate – [0040]);
forming a first dielectric layer (12 – [0048]) over the resistive layer (9);
forming a metallic barrier layer (17 – formed of Ru – [0049]) contacting the resistive layer (9) through an opening (opening in layer 10) in the first dielectric layer (12); and
forming a conductive via ({18, 19} – [0038], [0050]) that extends to the metallic barrier layer (17) through a second dielectric layer (14 – [0048]) over the resistive layer (9), the metallic barrier layer (17) contacting the conductive via ({18, 19}) and the resistive layer (9).
Regarding Claim 12, Saito teaches the method of claim 11, wherein the metallic barrier layer (17) comprises a barrier material (formed of Ru – [0049]), and the barrier material surrounds the conductive via ({18, 19}).
Regarding Claim 20, Saito teaches a method (see the entire document; Figs. 1-2; specifically, ([0038] - [0050]), and as cited below), comprising:
forming a first dielectric layer (1 – Fig. 1 – [0040]) over a semiconductor substrate (silicon substrate – [0040]);
forming a resistive layer (9 – Fig. 1 - [0038]) over the first dielectric layer (1);
forming a second dielectric layer (12 – [0048]) over the resistive layer (9);
patterning the second dielectric layer (12) to form header trenches over header regions of the resistive layer (trench in layer 10), a remaining portion of the second dielectric layer covering a resistor body spanning between the header regions of the resistive layer (see Fig. 1);
forming a metallic barrier layer (17 – formed of Ru – [0049]) in the header trenches (trench in 10);
depositing an inter-level dielectric (ILD) layer (14 - – [0048]) over the header trenches and the remaining portion of the second dielectric layer (12);
forming vias (18 – [0038]) in or through the ILD layer (14), the vias each landing on the metal barrier layer (17) in respective header trenches (trench); and
forming metal interconnect traces (19 – [0050]) over and in electrical contact with the vias (18), the metal interconnect traces (19) and the vias (18) surrounded by a same barrier material (Ru – [0049]) as the metallic barrier layer (17).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Saito in view of Noda et al. (US 20110215473 A1 - hereinafter Noda).
Regarding Claim 13, Saito teaches claim 12 from which claim 12 depends. But Saito does not expressly disclose wherein the barrier material comprises a material selected from the group consisting of TaN, Ta, Ta-Si-N, W, W-N, and W-Si-N.
However, it is well known in the art to form metal barrier layers formed of Tantalum, TaN as is also taught by Noda (Noda – [0035] – “For example, the barrier metal layer 6 is formed of tantalum (Ta), tantalum nitride (TaN)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming of the metal barrier layer of tantalum as taught by Noda into Saito.
An ordinary artisan would have been motivated to integrate Noda structure into Saito structure in the manner set forth above for the obvious benefit of enhanced diffusion resistance and low electrical resistivity.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Saito in view of Kande et al. (US 20190139861 A1 - hereinafter Kande).
Regarding Claim 14, Saito teaches claim 11 from which claim 14 depends. But Saito does not expressly disclose wherein the resistive layer comprises silicon chromium (SiCr).
However, it is well known in the art to form resistive layer of silicon chromium as is also taught by Kande (Kande – [0040] – “resistor 228 may be formed on the IMD layer 216. The resistor 228 may include a body layer formed by sputtering a thin film layer of resistive material such as nickel chromium, silicon chromium, tantalum nitride, or such”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming wherein the resistive layer comprises silicon chromium as taught by Kande into Saito.
An ordinary artisan would have been motivated to integrate Kande structure into Saito structure in the manner set forth above for the obvious benefit of high electrical stability and low temperature coefficient.
Allowable Subject Matter
Claims 15-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 15: The method of claim 11, wherein the opening is formed over a header end of the resistive layer, and further comprising forming a dielectric barrier layer over the metallic barrier layer in the opening before forming the second dielectric layer.
Claim 16 depends from claim 15.
Regarding claim 17: The method of claim 11, wherein the conductive via is a first conductive via, and further comprising forming a second conductive via extending from an upper metal interconnect trace through the second dielectric layer and the first dielectric layer to a metal interconnect trace below the resistive layer.
Claim 18 depends from claim 17.
Regarding claim 19: The method of claim 11, wherein the first and second dielectric layers comprise material layers having an etch rate higher than an etch rate of the metallic barrier layer during via etch.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898
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