DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 04/29/24 & 06/25/26 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 7-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sundaram et al. (US 2012/0106117, cited on IDS).
a. Re claim 1, Sundaram et al. disclose a semiconductor device assembly comprising: a first semiconductor device (stack of memory devices on fig. 32 and related text; see [0005]-[0009], [0064] and remaining of disclosure for more details) having a first footprint (this is implicit since the stack of memory device is a three dimensional structure); a second semiconductor device (top logic device on fig. 32 and related text; see [0005]-[0009], [0050], [0063]-[0067]) having a second footprint (implicit since the logic device is a three dimensional structure); an interposer (unlabeled interposer on which the logic devices and memory devices are stacked on; see for example figs.6-28 and related text for more details on said interposer) comprising: a substrate (glass substrate on fig. 7 for example, and as applied in fig. 32) having a first (top) surface carrying the first semiconductor device in a first region (region corresponding to the footprint of the stacked memory devices) and the second semiconductor device in a second region (region corresponding to the footprint of the top logic device), the substrate having a second (bottom) surface opposite the first surface; first and second pluralities of through-substrate vias (unlabeled Cu through-vias on fig. 32; the first plurality of through-substrate vias are the through-substrate vias in the footprint of the stacked memory devices on fig. 32, the second plurality of through-substrate vias are the ones in the footprint of the top logic device), each through-substrate via including an exposed portion (portion out of the glass substrate as per fig. 7) and an embedded portion (explicit on fig. 7), the exposed portions projecting from the second surface of the substrate and the embedded portions extending through at least a portion of the substrate between the first surface and the second surface (explicit on fig. 7), the first plurality of through-substrate vias vertically aligned with the first footprint (explicit on fig. 32) and operably coupled to the first semiconductor device, the second plurality of through-substrate vias vertically aligned with the second footprint and operably coupled to the second semiconductor device (explicit on fig. 32).
b. Re claim 2, the first semiconductor device is comprised by a stack of memory dies (explicit on fig. 32).
c. Re claim 3, the second semiconductor device is a memory controller (explicit on fig. 32 noting that the logic device controls the operation of the memory devices).
d. Re claim 7, Sundaram et al. disclose a semiconductor device assembly comprising: a first semiconductor device (stack of memory devices on fig. 32 and related text; see [0005]-[0009], [0064] and remaining of disclosure for more details) having a first footprint (implicit since the stack of memory device is a three dimensional structure); a second semiconductor device (top logic device on fig. 32) having a second footprint (implicit since the logic device is a three dimensional structure); an interposer (unlabeled interposer on which the logic devices and memory devices are stacked on; see for example figs.6-28 and related text for more details on said interposer) comprising: a substrate (glass substrate on fig. 7 for example, and as applied in fig. 32) having a first (top) surface carrying the first semiconductor device in a first region (region corresponding to the footprint of the stacked memory devices) and the second semiconductor device in a second region (region corresponding to the footprint of the top logic device), the substrate having a second (bottom) surface opposite the first surface; first and second pluralities of through-substrate vias (unlabeled Cu through-vias on fig. 32; the first plurality of through-substrate vias are the through-substrate vias in the footprint of the stacked memory devices on fig. 32, the second plurality of through-substrate vias are the ones in the footprint of the top logic device), each through-substrate via including an exposed portion (portion out of the glass substrate on fig. 7) and an embedded portion (portion within the glass substrate), the exposed portions projecting from the first surface of the substrate and the embedded portions extending through at least a portion of the substrate between the first surface and the second surface (explicit on fig. 7), the first plurality of through-substrate vias vertically aligned with the first footprint and operably coupled to the first semiconductor device (explicit on fig. 32), the second plurality of through-substrate vias vertically aligned with the second footprint and operably coupled to the second semiconductor device (explicit on fig. 32).
e. Re claims 8 and 9, see respectively claims 2 and 3 rejections above.
f. Re claim 10, the semiconductor device assembly of claim 7, further comprises a third semiconductor device (bottom logic device on fig. 32) carried by the second surface of the substrate of the interposer.
Claim(s) 1, 6-7 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Akram et al. (US 2006/0046468).
a. Re claim 1, Akram et al. disclose a semiconductor device assembly comprising: a first semiconductor device 42 (see fig. 27 and related text; see [0094] and remaining of disclosure for more details) having a first footprint (implicit since die 42 is a three dimensional structure); a second semiconductor device 42a having a second footprint (implicit since die 42 is a three dimensional structure); an interposer 50y ([0094]) comprising: a substrate 60&128 ([0068], [0083]) having a first (top) surface carrying the first semiconductor device in a first region (region corresponding to the footprint of die 42) and the second semiconductor device in a second region (region corresponding to the footprint of die 42a), the substrate having a second (bottom) surface opposite the first surface; first and second pluralities of through-substrate vias 70 ([0066]; the first plurality of through-substrate vias are the through-substrate vias in the footprint of die 42, and the second plurality of through-substrate vias are the through-substrate vias in the footprint of die 42a), each through-substrate via including an exposed portion and an embedded portion (explicit on fig. 27), the exposed portions projecting from the second surface of the substrate and the embedded portions extending through at least a portion of the substrate between the first surface and the second surface (explicit on fig. 27), the first plurality of through-substrate vias vertically aligned with the first footprint and operably coupled to the first semiconductor device (explicit on fig. 27), the second plurality of through-substrate vias vertically aligned with the second footprint and operably coupled to the second semiconductor device (explicit on fig. 27).
b. Re claim 6, the second surface of the substrate of the interposer is defined by an outer surface of a layer of underfill or of nonconductive film 128 ([0083]).
c. Re claim 7, Akram et al. disclose a semiconductor device assembly comprising: a first semiconductor device 42 (see fig. 27 and related text; see [0094] and remaining of disclosure for more details) having a first footprint (as explained above); a second semiconductor device 42a having a second footprint (as explained above); an interposer 50y comprising: a substrate 60&128 having a first (top) surface carrying the first semiconductor device in a first region (region corresponding to the footprint of die 42) and the second semiconductor device in a second region (region corresponding to the footprint of die 42a), the substrate having a second (bottom) surface opposite the first surface; first and second pluralities of through-substrate vias 70 ([0066]; the first plurality of through-substrate vias are the through-substrate vias in the footprint of die 42, and the second plurality of through-substrate vias are the through-substrate vias in the footprint of die 42a), each through-substrate via including an exposed portion and an embedded portion (explicit on fig. 27), the exposed portions projecting from the first surface of the substrate and the embedded portions extending through at least a portion of the substrate between the first surface and the second surface (explicit on fig. 27), the first plurality of through-substrate vias vertically aligned with the first footprint and operably coupled to the first semiconductor device (explicit on fig. 27), the second plurality of through-substrate vias vertically aligned with the second footprint and operably coupled to the second semiconductor device (explicit on fig. 27).
d. Re claim 13, the first surface of the substrate of the interposer is defined by an outer surface of a layer of underfill or of nonconductive film 128 ([0083]).
Claim(s) 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Colgan et al. (US 2007/0232090, cited on IDS).
Re claim 14, Colgan et al. disclose an interposer 120 (see fig. 1B and related text; see remaining of disclosure for more details) comprising: a substrate 121 ([0008]) having a first (top) surface including a first plurality of electrical contacts (two top connectors 122a starting from right to left on fig. 1B) “configured to electrically couple directly to a first semiconductor device” (the limitation “configured to electrically couple directly to a first semiconductor device” does not structurally distinguish over connectors 122a but merely convey the capability of being coupled to a first semiconductor device whose presence is not required by the claim language; the two top connectors mentioned above are capable of being electrically directly coupled to a semiconductor device which basically the package 100 is), and a second (bottom) surface opposite the first surface and spaced from the first surface by a thickness of the substrate (explicit on fig. 1B); and a plurality of through-substrate vias (structures 122 including their portions extending in holes 122c and which are on the left of the first plurality of electrical contacts defined above; see at least [0008]), each through-substrate via including an exposed portion 122b and an embedded portion (portion in hole 122c), the exposed portions projecting from the second surface of the substrate by a distance greater than the thickness of the substrate (explicit on fig. 1B), and the embedded portions extending through at least a portion of the substrate between the first surface and the second surface (explicit on fig. 1B).
Allowable Subject Matter
Claims 4-5, 11-12 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM.
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/PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899
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