DETAILED ACTION
This office action is in response to the application filed on April 29, 2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 4/29/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9, 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Inoue (US 2020/0205292).
With respect to Claim 1, Inoue discloses (Fig. 1-5c) all aspects of the current invention including a semiconductor device comprising:
a circuit board (2), including: an interconnect plate (plate 20), and a semiconductor element (3) disposed on the interconnect plate;
a case member (11), having: a housing portion (opening of lowermost portions (12) of the case 11 surrounding 2; see par 28) in which the circuit board is disposed, and a terminal arrangement portion (13), which is adjacent to the housing portion in a plan view of the semiconductor device, the terminal arrangement portion having: a first surface (top) and a second surface (bottom) opposite to each other, and a wall surface (13a) facing the housing portion;
a plurality of main terminals (15 left, 15 right), each having: an outer terminal portion (15b) exposed from the terminal arrangement portion, and an inner terminal portion (15a) electrically connected to the circuit board, wherein the plurality of main terminals includes a first main terminal (15 left) and a second main terminal (15 right), the outer terminal portions of which are arranged with a predetermined gap therebetween in a first direction (x direction);
the terminal arrangement portion of the case member includes:
a recess (opening of uppermost portions of the case 11; see Fig 1, 3) that is formed in the first surface thereof between the outer terminal portion (15b left) of the first main terminal and the outer terminal portion (15b right) of the second main terminal and that extends in a second direction (y direction) different from the first direction, wherein in the second direction, each of the outer terminal portions has a first end portion and a second end portion, the first end portion being closer to the housing portion than the second end portion, and the recess has a first end and a second end, the first end being closer to the housing portion than the second end thereof, and than the first end portion of the outer terminal portion of the first main terminal and the first end portion of the outer terminal portion of the second main terminal, and the second end being farther from the housing portion than the second end portion of the outer terminal portion of the first main terminal and the second end portion of the outer terminal portion of the second main terminal
a protrusion (17) formed on the wall surface thereof toward the housing portion, the protrusion being aligned with the recess in the second direction and separating the recess and the housing portion
With respect to Claim 2, Inoue discloses (Fig. 1-5c) wherein the terminal arrangement portion of the case member includes a stepped portion protruding from the wall surface to thereby form the protrusion (see fig 3)
With respect to Claim 3, Inoue discloses (Fig. 1-5c) wherein the first end of the recess reaches a surface of the stepped portion.
With respect to Claim 4, Inoue discloses (Fig. 1-5c) wherein the recess includes an end section that is located between the housing portion and the first end portions of the outer terminal portions of the first and second main terminals in the second direction, and a width of the end section in the first direction is larger than that of a section of the recess other than the end section.
With respect to Claim 5, Inoue discloses (Fig. 1-5c) wherein the first surface of the terminal arrangement portion has a first region (W1) in which the outer terminal portion of the first main terminal is arranged, and a second region (W1) in which the outer terminal portion of the second main terminal is arranged, the first and second regions being separated by the recess.
With respect to Claim 6, Inoue discloses (Fig. 1-5c) wherein the first surface of the terminal arrangement portion includes a first region in which the outer terminal portion of the first main terminal is arranged, a second region in which the outer terminal portion of the second main terminal is arranged, and a third region (W2) connecting the first region and the second region, the third region being located closer to the housing portion than the first end of the recess.
With respect to Claim 7, Inoue discloses (Fig. 1-5c) wherein the recess includes an end section that is located between the housing portion and the first end portions of the outer terminal portions of the first and second main terminals in the second direction, and in a thickness direction of the semiconductor device, a depth of the end section from the first surface is shallower than that of a section of the recess other than the end section.
With respect to Claim 8, Inoue discloses (Fig. 1-5c) wherein in a thickness direction of the semiconductor device, the semiconductor element (3) is disposed closer to the first surface (top surface) of the terminal arrangement portion (13) than the interconnect plate (plate 20), and the protrusion (17) is located closer to the first surface than the interconnect plate.
With respect to Claim 9, Inoue discloses (Fig. 1-5c) wherein a protruding amount of the protrusion decreases in the thickness direction of the semiconductor device.
With respect to Claim 12, Inoue discloses (Fig. 1-5c) wherein the case member has a substantially annular shape, a hollow portion thereof forming the housing portion.
With respect to Claim 13, Inoue discloses (Fig. 1-5c) , further comprising a cooler (par 19; cooler or cooling fin in base 10) thermally connected to a first surface of the interconnect plate, which is opposite to a second surface of the interconnect plate on which the semiconductor element is disposed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Inoue (US 2020/0205292) in view of Nakayama (US 2021/0013141).
With respect to Claim 10, Inoue discloses (Fig. 1-5c) most aspects of the current invention. However, Inoue does not show wherein the circuit board is formed with an inverter circuit having a first input end, a second input end, and an output end, and the first main terminal is electrically connected to the first input end of the inverter circuit, and the second main terminal is electrically connected to the second input end of the inverter circuit.
On the other hand, and in the same field of endeavor, Nakayama teaches (Fig 1-14) a semiconductor device comprising a circuit board (162), including: an interconnect plate (161), and a semiconductor element (78,79) disposed on the interconnect plate, a case member (88), having a housing portion in which the circuit board is disposed, and a terminal arrangement portion (88), which is adjacent to the housing portion in a plan view of the semiconductor device, a plurality of main terminals (86), each having: an outer terminal portion (199) exposed from the terminal arrangement portion, and an inner terminal portion (15a) electrically connected to the circuit board and further wherein the circuit board is formed with an inverter circuit (inverter circuit) having a first input end (U-phase), a second input end (V-phase), and an output end (W-phase), and a first main terminal is electrically connected to the first input end of the inverter circuit, and a second main terminal is electrically connected to the second input end of the inverter circuit. Nakayama teaches doing so to allow the semiconductor module to function as a three-phase AC inverter circuit having output terminals (par 130)
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein the circuit board is formed with an inverter circuit having a first input end, a second input end, and an output end, and the first main terminal is electrically connected to the first input end of the inverter circuit, and the second main terminal is electrically connected to the second input end of the inverter circuit in the device of Inoue, as taught by Nakayama to allow the semiconductor module to function as a three-phase AC inverter circuit having output terminals.
With respect to Claim 11, Nakayama teaches (Fig 1-14) wherein the plurality of main terminals further includes a third main terminal, the third main terminal, and the first and second main terminals, are arranged with the housing portion interposed therebetween, and the third main terminal is electrically connected to the output end of the inverter circuit.
With respect to Claim 14, Nakayama teaches (Fig 1-14) a vehicle comprising a semiconductor device according to the semiconductor module of Inoue in view of Nakayama (see par 128-130 and Fig 13). Also, see comments stated above in Par. 22-23 with regards to Claim 10, which are considered repeated here.
Conclusion
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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