Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 04/29/24. Claims 1-17 are pending in this application.
Information Disclosure Statement
The information disclosure statement filed on 04/29/24 has been received and is being considered.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-17 are rejected under 35 U.S.C. §102(a)(1) as being unpatentable over Hong (US 20190355643 A1).
Regarding claim 1, Hong discloses The semiconductor device includes a semiconductor die 102,
a die pad (114) having a die mounting surface (128) and an outer surface (130). a first conductive lead [132]. The semiconductor device has an upper surface 120, a lower surface 122, and a side wall 124, and has an enclosure 118 made of plastic covering the semiconductor die 102 and a part of the die pad 114,
The outer surface 130 is exposed from the upper surface 120 and extends outward from the side wall 124 when viewed in the thickness direction [in particular. see paragraph [0035]].
Hong discloses the first lead including a die pad portion and a first terminal portion (see fig 2, 114), the die pad portion including a first lead obverse surface which faces a first side in a thickness direction and on which the semiconductor element is mounted (see fig 2, 114 having a top side), and a first lead reverse surface facing a second side in the thickness direction (see 2, 114 having an other side); and a sealing resin including a first resin surface facing the first side in the thickness direction (see 118 ), a second resin surface facing the second side in the thickness direction (see 118 has a bottom resin surface), and a third resin surface facing a first side in a first direction orthogonal to the thickness direction (side surfaces of 118), the sealing resin covering the semiconductor element and a part of the die pad portion(see 102 is covered by 118 on all sides), wherein the first lead reverse surface includes a portion exposed from the second resin surface and located on the first side in the first direction from the third resin surface as viewed in the thickness direction (see fig 3 where leads 136 and 142 extending out).
Regarding claim 2, Hong discloses the semiconductor device according to claim 1, wherein the first lead reverse surface is flush with the second resin surface (see figs 2a and b disclosing 130 is flush with top resin).
Regarding claim 3, Hong discloses the semiconductor device according to claim 1, wherein the die pad portion includes a first lead side surface facing the first side in the first direction, and the first lead side surface is located on the first side in the first direction from the third resin surface (see 144/146 flush with bottom 122).
Regarding claim 4, Hong discloses the semiconductor device according to claim 3, wherein the first terminal portion includes a first portion extending outward from the third resin surface toward the first side in the first direction (see 144/146 extending out from the sides).
Regarding claim 5, Hong discloses the semiconductor device according to claim 4, wherein the first terminal portion includes a second portion located on the first side in the thickness direction with respect to the first portion and used for mounting (see 158/154).
Regarding claim 6, Hong discloses the semiconductor device according to claim 5, wherein the first terminal portion includes a third portion interposed between the first portion and the second portion (see figs 2 and 3 disclosing die pad on top and being between top and bottom).
Regarding claim 7, Hong discloses the semiconductor device according to claim 6, wherein the third portion extends from the first portion toward the first side in the thickness direction (see figs 1 and 2 disclosing extension integrally conductive structure 164).
Regarding claim 8, Hong discloses the semiconductor device according to claim 5, wherein the first lead includes plurality of first terminal portions (see fig 2, disclosing 138, 132).
Regarding claim 9, Hong discloses the semiconductor device according to claim 8, wherein the plurality of first terminal portions are arranged side by side in a second direction orthogonal to the thickness direction and the first direction (see figs 2 and 3 disclosing orthogonal and side-by side arrangement).
Regarding claim 10, Hong discloses the semiconductor device according to claim 5, wherein the die pad portion is larger than the first portion of the first terminal portion in size in the thickness direction (see figs 2 and 3 disclosing exposed die pad 130 having thickness larger than terminal 136).
Regarding claim 11, Hong discloses the semiconductor device according to claim 10, wherein one face of the first portion is flush with the first lead obverse surface (see fig 2, disclosing 130 being flush).
Regarding claim 12, Hong discloses the semiconductor device according to claim 5, further comprising:
a connecting member connected to the semiconductor element (see 106, 108, 102); and a second lead located on a second side in the first direction with respect to the first lead and including a pad portion that includes a second lead obverse surface facing the first side in the thickness direction(see second lead 142), wherein the connecting member is connected to the second lead obverse surface (see bond wires 115), and the first lead obverse surface and the second lead obverse surface are at a same position in the thickness direction (see fig 3 disclosing uniform thickness of 142/146).
Regarding claim 13, Hong discloses the semiconductor device according to claim 12, wherein the sealing resin includes a fourth resin surface facing the second side in the first direction (see 166 sealed on all sides), and the second lead includes a second terminal portion including a fourth portion penetrating the fourth resin surface (see terminals 134/140 penetrating resin).
Regarding claim 14, Hong discloses the semiconductor device according to claim 13, wherein the second terminal portion includes a fifth portion located on the first side in the thickness direction with respect to the fourth portion and used for mounting, and a sixth portion interposed between the fourth portion and the fifth portion(see flat portions of leads 158).
Regarding claim 15, Hong discloses the semiconductor device according to claim 14, wherein the second portion of the first terminal portion and the fifth portion of the second terminal portion are located on the second side in the thickness direction from the first resin surface (see 154/158, fig 3).
Regarding claim 16, Hong discloses the semiconductor device according to claim 1, wherein the sealing resin includes a groove recessed from the second resin surface in the thickness direction (see groove where 130 sits in fig 2 and indentations in 130).
Regarding claim 17, Hong discloses the semiconductor device according to claim 1, wherein the sealing resin includes a protrusion that protrudes from the second resin surface in the thickness direction(see groove where 130 sits in fig 2 and indentations in 130).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
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