Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,5-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Toyoda et al. (hereinafter Toyoda, US 2015/0311339).
In regards to independent claim 1, Toyoda teaches a transistor comprising:
a first well region doped with second type dopants (Toyoda, Fig. 12 P-Type Item 2);
a second well region doped with first type dopants (Toyoda, Fig. 12 N-Type Item 16);
a third well region (Toyoda, Fig. 12 Item 6);
a first isolation structure neighboring the first well region (Toyoda, Fig. 12 LOCOS 7);
a second isolation structure neighboring the the second well region and the third well region (Toyoda, Fig. 12 Central LOCOS 7);
a drain region doped with the first type dopants disposed in the third well region (Toyoda, Fig. 12 N-Type Item 5,6);
a source region doped with the first type dopants disposed in the first well region (Toyoda, Fig. 12 N-Type Item 3,2); and
a gate disposed at least partially over the second isolation structure, wherein the transistor is configured as a depletion mode transistor (Toyoda, Fig. 12 Item 9,7 [0033]).
In regards to dependent claim 5, Toyoda teaches wherein the drain region is a shared drain region (Toyoda, Fig. 12 N-Type Item 5,6, clarify what it is shared with).
In regards to dependent claim 6, Toyoda teaches wherein the first and second isolation structures have a depth, the depth being less than depths of the second well region and the first well region (Toyoda, Fig. 12 Item 7 vs, 2, 16).
In regards to dependent claim 7, Toyoda teaches comprising:
an undoped region between a bottom of the first well region and the third well region and between the second well region and the third well region (Lee, Fig. 4 Item 420, Column 5 Lines 35-60).
In regards to independent claim 8, Toyoda teaches wherein the third well region is doped with N type dopants (Toyoda, Fig. 12 Item 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4, 9-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toyoda in view of Lee et al. (hereinafter Lee, US 7,592,661).
In regards to dependent claim 2, Toyoda fails to teach wherein a first distance in the first well region between the source region and an undoped region is between 0 and 150 nanometers. Lee teaches
wherein a first distance in the first well region between the source region and an undoped region is between 0 and 150 nanometers (Lee, Fig. 4 Item 420, Column 5 Lines 35-60).
It would have been obvious to one of ordinary skill in the art, having the teachings of Toyoda and Lee before him before the effective filing date of the claimed invention, to modify transistor taught by Toyoda to include the undoped separation area of Lee in order to obtain a transistor whose wells are separated by an undoped region One would have been motivated to make such a combination because it reduces leakage from one well to another.
In regards to dependent claim 3, Toyoda fails to teach wherein a second distance in the undoped region between the first well region and the second well region is between 0 and 200 nanometers. Lee teaches
wherein a second distance in the undoped region between the first well region and the second well region is between 0 and 200 nanometers. (Lee, Fig. 4 Item 420, Column 5 Lines 35-60). It would have been obvious to one of ordinary skill in the art, having the teachings of Toyoda and Lee before him before the effective filing date of the claimed invention, to modify transistor taught by Toyoda to include the undoped separation area of Lee in order to obtain a transistor whose wells are separated by an undoped region One would have been motivated to make such a combination because it reduces leakage from one well to another.
In regards to dependent claim 4, Toyoda fails to teach wherein a first distance in an undoped region between the first well region and the second well region is between 0 and 200 nanometers. Lee teaches
wherein a first distance in an undoped region between the first well region and the second well region is between 0 and 200 nanometers. (Lee, Fig. 4 Item 420, Column 5 Lines 35-60). It would have been obvious to one of ordinary skill in the art, having the teachings of Toyoda and Lee before him before the effective filing date of the claimed invention, to modify transistor taught by Toyoda to include the undoped separation area of Lee in order to obtain a transistor whose wells are separated by an undoped region One would have been motivated to make such a combination because it reduces leakage from one well to another.
In regards to independent claim 9, Toyoda teaches an integrated circuit, comprising:
a first well region doped with second type dopants (Toyoda, Fig. 12 P-Type Item 2);
a second well region doped with first type dopants (Toyoda, Fig. 12 N-Type Item 16);
a third well region (Toyoda, Fig. 12 Item 6);
a drain region doped with the first type dopants disposed in the third well region (Toyoda, Fig. 12 N-Type Item 5,6);
a source region doped with the first type dopants disposed in the first well region (Toyoda, Fig. 12 N-Type Item 3,2); and
a gate disposed between the source region and the drain region (Toyoda, Fig. 12 Item 9,7 [0033]).
Toyoda fails to teach
wherein a first distance in the first well region between the source region and an undoped region is between 0 and 150 nanometers. Lee teaches wherein a first distance in the first well region between the source region and an undoped region is between 0 and 150 nanometers (Lee, Fig. 4 Item 420, Column 5 Lines 35-60). It would have been obvious to one of ordinary skill in the art, having the teachings of Toyoda and Lee before him before the effective filing date of the claimed invention, to modify transistor taught by Toyoda to include the undoped separation area of Lee in order to obtain a transistor whose wells are separated by an undoped region One would have been motivated to make such a combination because it reduces leakage from one well to another.
In regards to dependent claim 10, Toyoda fails to teach wherein a second distance in the undoped region between the first well region and the second well region is between 0 and 200 nanometers
10. The integrated circuit of claim 9, wherein a second distance in the undoped region between the first well region and the second well region is between 0 and 200 nanometers. (Lee, Fig. 4 Item 420, Column 5 Lines 35-60).. It would have been obvious to one of ordinary skill in the art, having the teachings of Toyoda and Lee before him before the effective filing date of the claimed invention, to modify transistor taught by Toyoda to include the undoped separation area of Lee in order to obtain a transistor whose wells are separated by an undoped region One would have been motivated to make such a combination because it reduces leakage from one well to another.
In regards to dependent claim 11, Toyoda teaches:
a first isolation structure neighboring the first well region; a second isolation structure neighboring the the second well region and the third well region (Toyoda, Fig. 12 Central LOCOS 7).
In regards to dependent claim 12, Toyoda teacheswherein the drain region is a shared drain region (Toyoda, Fig. 12 N-Type Item 5,6, clarify what it is shared with).
In regards to dependent claim 14, Toyoda teaches wherein the undoped region between a bottom of the first well region and the third well region and between the second well region and the third well region (Lee, Fig. 4 Item 420, Column 5 Lines 35-60). It would have been obvious to one of ordinary skill in the art, having the teachings of Toyoda and Lee before him before the effective filing date of the claimed invention, to modify transistor taught by Toyoda to include the undoped separation area of Lee in order to obtain a transistor whose wells are separated by an undoped region One would have been motivated to make such a combination because it reduces leakage from one well to another.
In regards to dependent claim 15, Toyoda teaches wherein the third well region is doped with N type dopants (Toyoda, Fig. 12 Item 6).
In regards to independent claim 16, Toyoda teaches a method comprising:
forming a first well region doped with first type dopants above the deep well, the first type dopants being one of the N type dopants or P type dopants (Toyoda, Fig. 12 P-Type Item 2);
forming a second well region doped with second type dopants above the deep well, the second type dopants being the other of the N type dopants or the P type dopants (Toyoda, Fig. 12 N-Type Item 16);
forming a first shallow trench isolation structure (Toyoda, Fig. 12 Central LOCOS 7);
forming a gate (Toyoda, Fig. 12 Item 9,7 [0033]);
forming a source region between the gate and the first shallow trench isolation structure above the first well region (Toyoda, Fig. 12 N-Type Item 3,2); and
forming a drain region in the second well region (Toyoda, Fig. 12 N-Type Item 5,6).
Toyoda fails to explicitly teach:
providing a deep well doped with N type dopants;
wherein a first distance in the first well region between the source region and an undoped region is between 0 and 150 nanometers.
Lee teaches:
providing a deep well doped with N type dopants (Lee, 514, Column 4 Lines 36-46);
wherein a first distance in the first well region between the source region and an undoped region is between 0 and 150 nanometers (Lee, Fig. 4 Item 420, Column 5 Lines 35-60). It would have been obvious to one of ordinary skill in the art, having the teachings of Toyoda and Lee before him before the effective filing date of the claimed invention, to modify transistor taught by Toyoda to include the undoped separation area of Lee in order to obtain a transistor whose wells are separated by an undoped region One would have been motivated to make such a combination because it reduces leakage from one well to another.
In regards to dependent claim 17, Toyoda fails to teach wherein a second distance in the undoped region between the first well region and the second well region is between 0 and 200 nanometers. Lee teaches wherein a second distance in the undoped region between the first well region and the second well region is between 0 and 200 nanometers. (Lee, Fig. 4 Item 420, Column 5 Lines 35-60). It would have been obvious to one of ordinary skill in the art, having the teachings of Toyoda and Lee before him before the effective filing date of the claimed invention, to modify transistor taught by Toyoda to include the undoped separation area of Lee in order to obtain a transistor whose wells are separated by an undoped region One would have been motivated to make such a combination because it reduces leakage from one well to another.
In regards to dependent claim 18, Toyoda teaches:
forming a second shallow trench isolation structure neighboring the second well region and the drain region. (Toyoda, Fig. 12 Item 7 vs, 2, 16).
In regards to dependent claim 19 Toyoda fails to teach wherein the undoped region is between the first well region and the deep well. Lee teaches wherein the undoped region is between the first well region and the deep well (Lee, Fig. 4 Item 420, Column 5 Lines 35-60). It would have been obvious to one of ordinary skill in the art, having the teachings of Toyoda and Lee before him before the effective filing date of the claimed invention, to modify transistor taught by Toyoda to include the undoped separation area of Lee in order to obtain a transistor whose wells are separated by an undoped region One would have been motivated to make such a combination because it reduces leakage from one well to another.
In regards to dependent claim 20 Toyoda teaches wherein the second well region is provided in a third well region doped with the other dopants of the N type dopants or the P type dopants (Toyoda, Fig. 12 Item 6).
Conclusion
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/WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812
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