Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
GUARD-RING OF A MEMORY CHIP AND MANUFACTURING METHOD OF THE GUARD-RING OF THE MEMORY CHIP
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 and 11-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. [US PGPUB 20150303214] (hereinafter Kim).
Regarding claim 1, Kim teaches a memory chip, comprising:
a memory region (I, Para 112) including cell plugs (230/235/240) in which data is stored (in view of structure 230, Para 122); and
a guard-ring (structure 250 in region II, Fig. 11B) surrounding the memory region (Para 112; in view of structure 250 formed in opening 217, and opening 217 surrounds the memory region),
the guard-ring includes sub-layers of the same materials arranged in the same order as layers forming the cell plugs (Fig. 8/10, Para 114/118).
Regarding claim 2, Kim teaches a memory chip wherein the sub-layers have a symmetrical structure with respect to a layer which is located at a center of the guard-ring (Fig. 11B).
Regarding claim 3, Kim teaches a memory chip wherein sub-layers contacting each other among the sub-layers include different materials from each other (Para 115/118/118).
Regarding claim 4, Kim teaches a memory chip wherein the sub-layers comprise:
first sub-layers (outer oxide layer of ONO layer 220 (230), Para 115) located at an outermost side of the guard-ring and facing each other (Fig. 8/11B);
second sub-layers (nitride layer of ONO layer 220 (230), Para 115) respectively contacting inner surfaces of the first sub-layers and facing each other (Fig. 8/11B);
third sub-layers (inner oxide layer of ONO layer 220 (230), Para 115) respectively contacting inner surfaces of the second sub-layers and facing each other (Fig. 8/11B);
fourth sub-layers (225 (235), Fig. 10/11B) respectively contacting inner surfaces of the third sub-layers and facing each other (Fig. 10/11B); and
a fifth sub-layer (240, Fig. 11B) located between the fourth sub-layers (Fig. 11B).
Regarding claim 5, Kim teaches a memory chip wherein the fifth sub-layer contacts inner surfaces of the fourth sub-layers (Fig. 11B).
Regarding claim 6, Kim teaches a memory chip wherein each of the first sub-layers, the third sub-layers, and the fifth sub-layer is an insulating layer (Para 115/227 –where layer 240 is as a result of deposited layer 227).
Regarding claim 7, Kim teaches a memory chip wherein the insulating layer is an oxide layer (Para 115).
Regarding claim 8, Kim teaches a memory chip wherein each of the second sub-layers is a nitride layer (Para 115).
Regarding claim 9, Kim teaches a memory chip wherein each of the fourth sub-layers is polysilicon (Para 118 –where layer 235 is as a result of deposited layer 225).
Regarding claim 11, Kim teaches a memory chip comprising:
a cell plug (230/235/240 in region I, Fig. 11B) including a first layer (outer oxide layer of ONO layer 220 (230), Para 115) penetrating a stack structure in a memory region (Fig. 11B, Para 59), a second layer (nitride layer of ONO layer 220 (230), Para 115) surrounded by the first layer (in view of layer 220 (230) being ONO stack), a third layer (inner oxide layer of ONO layer 220 (230), Para 115) surrounded by the second layer (in view of layer 220 (230) being ONO stack), a fourth layer (235, Fig. 11B) surrounded by the third layer (Fig. 11B), and a fifth layer surrounded by the fourth layer; and
a guard-ring (250, Para 83) located around the memory region (wherein material 250 is formed in opening 217 which surrounds the memory region),
wherein the guard-ring includes:
a first sub-layer (outer oxide layer of ONO layer 220 (232), Para 115) corresponding to the first layer (wherein 230 and 232 are formed from deposited material 220, Fig. 8);
a second sub-layer (nitride layer of ONO layer 220 (230), Para 115) surrounded by the first sub-layer (in view of layer 220 (232) being ONO stack) and corresponding to the second layer (wherein 230 and 232 are formed from deposited material 220, Fig. 8);
a third sub-layer (inner oxide layer of ONO layer 220 (230), Para 115) surrounded by the second sub-layer (in view of layer 220 (232) being ONO stack) and corresponding to the third layer (wherein 230 and 232 are formed from deposited material 220, Fig. 8);
a fourth sub-layer (237, Fig. 11B) surrounded by the third sub-layer (Fig. 11B) and corresponding to the fourth layer (wherein 237 and 235 are formed from material 225, (Para 118, Fig. 10); and
a fifth sub-layer (242, Fig. 11B) surrounded by the fourth sub-layer (Fig. 11B) and corresponding to the fifth layer (wherein 242 and 240 are formed from material 227, (Para 118, Fig. 10).
Regarding claim 12, Kim teaches a memory chip wherein in a cross-section of the guard-ring taken along a direction orthogonal to a direction in which the guard-ring extends, each of the first to fourth sub-layers has a tubular shape and the fifth sub-layer has a linear shape (Fig. 11B).
Regarding claim 13, Kim teaches a memory chip wherein each of the first layer, the third layer, the fifth layer, the first sub-layer, the third sub-layer, and the fifth sub-layer is an insulating layer (Para 115/118).
Regarding claim 14, Kim teaches a memory chip wherein the insulating layer is an oxide layer (Para 115/118).
Regarding claim 15, Kim teaches a memory chip wherein each of the second layer and the second sub-layer is a nitride layer (Para 115).
Regarding claim 16, Kim teaches a memory chip wherein each of the fourth layer and the fourth sub-layer is polysilicon (Para 118).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Tilke et al. [US PGPUB 20090001502] (hereinafter Tilke).
Regarding claim 10, Kim teaches the limitations of claim 1 upon which it depends.
Kim does not specifically disclose wherein a side of the guard-ring has a curved shape.
Referring to the invention of Tilke, Tilke teaches a guard ring structure 112, where the guard ring can be one of many shapes to include rounded or oval shape.
In view of such teaching by Tilke, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Kim comprise the teachings of Tilke (curved or oval ring, thus, side with curved shape) at least based on the rationale of simple substitution of one known element/structure with a suitable another to obtain predictable results (MPEP 2143.I.B).
Allowable Subject Matter
Claims 17-24 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 17-24 are allowed because all prior arts of record and related prior arts not of record either singularly or in combination fail to anticipate or render obvious a method of manufacturing a memory chip, the method comprising:
forming a stack structure over a lower structure in which a memory region and a guard region surrounding the memory region are defined;
increasing a width of the second opening and changing the second opening to a guard opening (as claimed in claim 17), in combination with the rest of claim limitations as claimed and defined by the Applicant.
Conclusion
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/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
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