DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-15 in the reply filed on 07/16/2026 is acknowledged.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/16/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, it is not clear how to reconcile the cited ranges of thicknesses, specifically, the thickness of the second semiconductor layer of 0.5 micrometers in both the diode and the IGBT regions with the limitation of claim 1, “wherein a thickness of the second semiconductor layer located in the IGBT region is greater than a thickness of the second semiconductor layer located in the diode region”.
Regarding claim 11, the limitation “between the IGBT region and the second semiconductor layer” in lines 2-3 is unclear, because the second semiconductor layer is also in the IGBT region, as shown in the drawings. Since this limitation is presented with an “or” linking, it is ignored for the purpose of Examination
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 7-9, and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsudai et. al., U.S. Pat. Pub. 2021/0091072, hereafter Matsudai.
Regarding claim 1, Matsudai discloses (Figs 1,2) a semiconductor device, comprising: a first-conductivity-type (n-type) first semiconductor layer [32], wherein the first semiconductor layer comprises a first (top) surface and a second (bottom) surface that are opposite to each other, and wherein the semiconductor device comprises (see Fig. 2) an insulated gate bipolar transistor (IGBT) comprising an IGBT region [102], and a diode comprising a diode region [102];
a second-conductivity-type second semiconductor layer [34], [38] disposed on the first surface of the first semiconductor layer [32], wherein (par. [0062]) a thickness (“depth”) of the second semiconductor layer [34] located in the IGBT region [101] is greater than a thickness (“depth”) of the second semiconductor layer [38] located in the diode region [102];
a first-conductivity-type (n-type) emitter region [36] (par. [0036]) disposed on a surface (top surface), of the second semiconductor layer [34] located in the IGBT region [101], that faces away from the first semiconductor layer [32]; and
a collector (par. [0031]) layer [28] and an electrode (par. [0031]) layer [30] that are disposed under the second (bottom) surface of the first semiconductor layer [32], wherein the collector layer and the electrode layer are respectively disposed in the IGBT region [101] and the diode region [102] (see Fig. 2).
Regarding claim 4, Matsudai further discloses (Figs 1,2) wherein the second semiconductor layer [34] located in the IGBT region [101] comprises a second-conductivity-type contact region [40], the semiconductor device comprises a plurality of emitter regions [36] disposed at intervals, the contact region [40] is disposed between two adjacent emitter regions [36], and a second-conductivity-type impurity concentration in the contact region [40] is greater than a second-conductivity-type impurity concentration in the second semiconductor layer [34] (par. [0066]).
Regarding claim 7, Matsudai further discloses (Figs 1,2, par. [0030]) further comprising: at least one gate electrode [51] that penetrates the second semiconductor layer [34] and that is in contact with the first semiconductor layer [32] in the IGBT region [101]; and
a first insulation layer [41] disposed between each gate electrode [51] of the at least one gate electrode and the first semiconductor layer [32].
Regarding claim 8, Matsudai further discloses (Figs 1,2) wherein one end (top surface) of the at least one gate electrode [51] is flush with a surface (top surface), of the emitter region [36], that faces away from the first semiconductor layer [32].
Regarding claim 9, Matsudai further discloses (Figs 1,2, par. [0030]) further comprising: at least one first electrode [53] that penetrates the second semiconductor layer [38] and that is in contact with the first semiconductor layer [32] located in the diode region [102]; and
a second insulation layer [43] disposed between each first electrode [53] of the at least one first electrode and the first semiconductor layer [32].
Regarding claim 13, Matsudai further discloses (Fig. 1, par. [0027]-[0029]) a power conversion circuit, comprising at least the semiconductor device according to claim 1.
Regarding claim 14, Matsudai further discloses (Figs 1,2, par. [0028]) a reverse conduction insulated gate bipolar transistor (RC-IGBT) chip [100], comprising at least the semiconductor device according to claim 1.
Regarding claim 15, Matsurai discloses (Figs 1,2, par. [0030]) an electronic device, comprising: a semiconductor device comprising:
a first-conductivity-type (n-type) first semiconductor layer [32], wherein the first semiconductor layer comprises a first (top) surface and a second (bottom) surface that are opposite to each other, and wherein the semiconductor device comprises an insulated gate bipolar transistor (IGBT) comprising an IGBT region [101], and a diode comprising a diode region [102];
a second-conductivity-type (p-type) second semiconductor layer [34],[38], disposed on the first (top) surface of the first semiconductor layer [32], wherein (par. [0062])a thickness (“depth”)of the second semiconductor layer [34] located in the IGBT region [101] is greater than a thickness (“depth”) of the second semiconductor layer [38] located in the diode region [102];
a first-conductivity-type emitter region [36] disposed on a surface (top surface), of the second semiconductor layer [34] located in the IGBT region [101], that faces away from the first semiconductor layer [32]; and
a collector layer [28] and an electrode layer [30] that are disposed under the second (bottom) surface of the first semiconductor layer [32], wherein the collector layer [28] and the electrode layer [30] are respectively disposed in the IGBT region [101] and the diode region [102].
Claims 1, 4-6, and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP2010-171057 (of record, with English translation supplied by the applicant), hereafter Denso.
Regarding claim 1, Denso discloses (Fig. 4, translated text of 3 bottom paragraphs of p.12 – 3 top par. of p.13) a semiconductor device, comprising: a first-conductivity-type (n-type) first semiconductor layer [10], wherein the first semiconductor layer comprises a first (top) surface and a second (bottom) surface that are opposite to each other, and wherein the semiconductor device comprises an insulated gate bipolar transistor (IGBT) comprising an IGBT region (Fig. 4, region “IGBT + FWD”), and a diode comprising a diode region (Fig. 4, region “2FWD”);
a second-conductivity-type (p-type) second semiconductor layer [14], [17], [24] disposed on the first (top) surface of the first semiconductor layer [10], wherein a thickness of the second semiconductor layer [14], [17] located in the IGBT region is greater than a thickness of the second semiconductor layer [24] located in the diode [2FWD] region (as shown in Fig. 4);
a first-conductivity-type (n+) emitter region [16] disposed on a surface (top surface), of the second semiconductor layer [14], [17] located in the IGBT region (IGBT +FWD), that faces away from the first semiconductor layer [10]; and
a collector layer [11] and an electrode layer [12] that are disposed under the second (bottom) surface of the first semiconductor layer [10], wherein the collector layer and the electrode layer are respectively disposed in the IGBT (IGBT + FWD) region and the diode (2FWD) region.
Regarding claim 4, Denso further discloses (Fig. 4, translated text of 3 bottom paragraphs of p.12 – 3 top par. of p.13) wherein the second semiconductor layer [14], [17] located in the IGBT region comprises a second-conductivity-type contact region [17], the semiconductor device comprises a plurality of emitter regions [16] disposed at intervals, the contact region [17] is disposed between two adjacent emitter regions [16], and a second-conductivity-type impurity concentration in the contact region [17] is greater than a second-conductivity-type impurity concentration in the second semiconductor layer [14] (p+ is a conventional notation of a heavily p-doped region which has a higher p-type impurity concentration than p-doped region).
Regarding claim 5, Denso further discloses (Fig. 4) wherein a difference between the thickness of the second semiconductor layer [14], [17] located in the IGBT region (IGBT +FWD) and the thickness of the second semiconductor layer [24] located in the diode region is not less than a thickness of the contact region [17] (the region [24] has a smaller thickness than [14] and lacks contact region [17]).
Regarding claim 6, Denso further discloses (Fig. 4) wherein the second semiconductor layer [24] located in the diode region [2FWD] does not comprise any second-conductivity-type contact region (as shown in Fig. 4, no p+ contact layer is present in region [2FWD]_.
Regarding claim 14, Denso further discloses (p. 7 of translation, par. 4 from the bottom) A reverse conduction insulated gate bipolar transistor (RC-IGBT) chip, comprising at least the semiconductor device according to claim 1.
Regarding claim 15, Denso discloses (Fig. 4, translated text of 3 bottom paragraphs of p.12 – 3 top par. of p.13) an electronic device, comprising: a semiconductor device comprising:
a first-conductivity-type (n-type) first semiconductor layer [10], wherein the first semiconductor layer comprises a first (top) surface and a second (bottom) surface that are opposite to each other, and wherein the semiconductor device comprises an insulated gate bipolar transistor (IGBT) comprising an IGBT region [IGBT+FWD], and a diode comprising a diode region [2FWD];
a second-conductivity-type (p-type) second semiconductor layer [14], [17], [24] disposed on the first (top) surface of the first semiconductor layer [10], wherein a thickness of the second semiconductor layer located in the IGBT region is greater than a thickness of the second semiconductor layer located in the diode region (see Fig.4, the thickness of layer [24] is smaller than the thickness of [14] alone, let alone [14] + [17]);
a first-conductivity-type (n-type) emitter region [16] disposed on a surface (top surface), of the second semiconductor layer [14]+[17] located in the IGBT region [IGBT+FWD], that faces away from the first semiconductor layer[10]; and
a collector layer [11] and an electrode layer [12] that are disposed under the second (bottom) surface of the first semiconductor layer [10], wherein the collector layer [11] and the electrode layer [12] are respectively disposed in the IGBT region [IGBT + FWD] and the diode region [2FWD].
Claims 1-2, 7-11, and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takahashi, U.S. Pat. Pub. 2008/0048295 (of record), hereafter Takahashi.
Regarding claim 1, Takahashi discloses (Figs 10,11) a semiconductor device, comprising: a first-conductivity-type (n-type, par. [0084]) first semiconductor layer [1], wherein the first semiconductor layer comprises a first (top) surface and a second (bottom) surface that are opposite to each other, and wherein the semiconductor device comprises an insulated gate bipolar transistor (IGBT) comprising an IGBT region [A], and a diode comprising a diode region [B];
a second-conductivity-type (p-type) second semiconductor layer [2], [2b] disposed on the first (top) surface of the first semiconductor layer [1], wherein a thickness of the second semiconductor layer [2] located in the IGBT region [A] is greater than a thickness of the second semiconductor layer [2b] located in the diode region [B] (See Figs 10,11;
a first-conductivity-type (n-type) emitter region [3] (see Fig. 1 for this label) disposed on a surface (tope surface), of the second semiconductor layer [2] located in the IGBT region [A], that faces away from the first semiconductor layer [1]; and
a collector layer [5] and an electrode layer [4] that are disposed under the second (bottom) surface of the first semiconductor layer [1], wherein the collector layer and the electrode layer are respectively disposed in the IGBT region [A] and the diode region [B] (See Figs 10,11).
Regarding claim 2,Takahashi further discloses (Figs 10,11, par. [0068]) wherein the thickness of the second semiconductor layer [2] located in the IGBT region [A] is in a range of 0.5 to 3 micrometers, and the thickness of the second semiconductor layer [2b] located in the diode region [B] is in a range of 0.5 to 2.5 micrometers.
Regarding claim 7, Takahashi further discloses (Figs 10,11, par. [0053]-[0056]) further comprising: at least one gate electrode [8] that penetrates the second semiconductor layer [2],[2b] and that is in contact with the first semiconductor layer [1] in the IGBT region [A]; and
a first insulation layer [7] disposed between each gate electrode [8] of the at least one gate electrode and the first semiconductor layer [1].
Regarding claim 8, Takahashi further discloses (Figs 10,11, par. [0053]-[0056]) wherein one end (top end) of the at least one gate electrode [8] is flush with a surface (top surface), of the emitter region [3] (see label in Fig. 1), that faces away from the first semiconductor layer [1].
Regarding claim 9, Takahashi further discloses (Figs 10,11, par. [0055]-[0056]) further comprising: at least one first electrode [8] that penetrates the second semiconductor layer [2b] and that is in contact with the first semiconductor layer [1] located in the diode region [B]; and
a second insulation layer [7] disposed between each first electrode [8] of the at least one first electrode and the first semiconductor layer [1].
Regarding claim 10, Takahashi further discloses (Figs 10,11, par. [0055]-[0056]) wherein one end (top end) of the at least one first electrode [8] is flush with the second semiconductor layer [2b] in the diode region [B].
Regarding claim 11, Takahashi further discloses (Fig. 11, par. [0079]) wherein a first-conductivity-type (n-type) carrier storage (CS) layer [13] is further comprised between the IGBT region and the second semiconductor layer or between the first semiconductor layer [1] and the second semiconductor layer [2],[2b].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi, U.S. Pat. Pub. 2008/0048295 (of record), hereafter Takahashi.
Regarding claim 3, Takahashi discloses everything as applied above. Denso fails to explicitly disclose wherein a ratio of the thickness of the second semiconductor layer located in the diode region to the thickness of the second semiconductor layer located in the IGBT region is in a range of 0.2 to 0.8.
However, It would have been obvious to one of ordinary skill in the art to arrive to this range by optimizing the relative thicknesses of the second semiconductor layer in the IGBT and the diode regions, because Takahashi teaches (par. [0088]-[0089]) that this is a result effective variable, and such optimization is done to reduce peak current of the recovery operation and improve the characteristics of the diode, and routine optimization of a result effective variable is normally considered to be obvious to one of ordinary skill in the art (MPEP, 2144.05.II.A,B, and case law therein).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi, U.S. Pat. Pub. 2008/0048295, hereafter Takahashi in view of CN103489908, hereafter ‘908 (of record, with English translation).
Regarding claim 12, Takahashi discloses everything as applied above. Takahashi fails to explicitly disclose
wherein the first semiconductor layer comprises at least one first-conductivity-type pillar and at least one second-conductivity-type pillar that are arranged alternately along a first direction, the first direction is perpendicular to a thickness direction, and both the first-conductivity-type pillar and the second-conductivity-type pillar extend along the thickness direction.
However, ‘908 discloses (Fig. 4) wherein the first semiconductor layer [6] comprises at least one first-conductivity-type pillar [6] and at least one second-conductivity-type pillar [7] that are arranged alternately along a first direction, the first direction is perpendicular to a thickness direction, and both the first-conductivity-type pillar and the second-conductivity-type pillar extend along the thickness direction.
It would have been obvious to one of ordinary skill in the art to modify the power IGBT of Takahashi with the teaching of superjunction IGBT of ‘908, because the superjunction drastically reduces on-resistance while maintaining a high breakdown voltage, which leads to faster switching.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm.
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/VICTOR V BARZYKIN/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
