DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 11-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/04/2026.
Applicant’s election without traverse of claims 1-10 in the reply filed on 08/04/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2,4-6 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Li, CN-107195613, and further in view of Love, US 5334804.
Regarding claims 1 and 10, Li discloses; An IC (integrated circuit) package comprising: a first interconnect (Fig. 1-3F; package substrate 110) comprising: a first surface comprising connection pads (Fig. 1-3F; copper pads 170, 171 on top surface of package substrate 110), wherein the connection pads include pillars extending in a direction normal to the first surface (Fig. 1-3F; copper column 180, 190 on the copper pads 170, 171); and a second surface opposing the first surface having connection pads for leads (Fig. 1-3F; external solder balls 120 located on the bottom surface of PCB package substrate 110); and a die mounted with solder bumps on the connection pads of the first surface of the first interconnect, wherein a portion of the solder bumps flow over the pillars (Fig. 1-3F; first chip 111 connected with first copper column 180 by flip-chip bonding and a second chip 112 connected with second copper column 190 through flip-chip bonding technique). Li substantially discloses the invention including PCB package substrate has first set of copper columns on top surface and external solder balls located on the bottom surface but is silent about a second interconnect comprising the leads mounted on the connection pads of the second surface of the first interconnect in claim 1 and a second set of pillars on the connection pads of the second surface of the first interconnect that extend in a direction normal to the second surface of the first interconnect in claim 10. However, Love teaches that second interconnect (major substrate 90) is electrically coupling on the bottom surface of first interconnect structure 200 , though Love does not particularly say about major substrate 90 has leads, while interconnect structure 200 used for coupling electrical signals and power between major substrate 90 and IC chip 70', therefore major substrate 90 has inherent leads for electrical signals and power (Fig. 5 and Col. 5; Ln 8-12). Also interconnect structure 200 has second set of interconnect columns 15b, 15d and 15f on the bottom surface 214 (Fig. 5 and Col. 5; Ln 22-23). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Li by providing a second interconnect comprising the leads mounted on the connection pads of the second surface of the first interconnect in claim 1 and a second set of pillars on the connection pads of the second surface of the first interconnect that extend in a direction normal to the second surface of the first interconnect in claim 10, so that the effects of thermal mechanical stress be reduced by having a large aspect ratio for each post and by having means disposed at one or both ends of each post for de-concentrating the mechanical stress and strain developed along the body of the post (Col. 4; Ln. 57-61).
Regarding claim 2, Li discloses; the connection pads and the pillars of the first surface of the first interconnect are formed with copper (Fig. 1-3F; copper column 180, 190 on the copper pads 170, 171).
Regarding claim 4, Li discloses; the portion of the solder bumps encase the copper pillars (Fig. 1-3F; first chip 111 connected with first copper column 180 by flip-chip bonding and a second chip 112 connected with second copper column 190 through flip-chip bonding technique).
Regarding claim 5, Li discloses; the pillars have a circular cross section (Fig. 1-3F; copper column 180, 190 on the copper pads 170, 171 and the diameter, height and other parameters meet the conventional flip-chip bonding technique).
Regarding claim 6, Li substantially discloses the invention including PCB package substrate has first set of copper columns on top surface with the diameter, height and other parameters meet the conventional flip-chip bonding technique but is specifically silent about the pillars have a diameter of about 5 to about 10 micrometers. However, Love teaches that post 14 has a base diameter of about 10 microns, a top diameter of about 15 microns, an average diameter of about 12.5 microns (Col. 7; Ln. 18-20). Similarly, a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close- MPEP 2144.05. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Li by providing the pillars have a diameter of about 5 to about 10 micrometers, so that the interconnect substrate further comprises a device for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post (abstract).
Regarding claim 8, Li discloses; each connection pad of the connection pads includes multiple pillars (Fig. 1-3F; multiple copper columns 180 on the copper pad 170).
Regarding claim 9, Li discloses; connection nodes on the die oppose the connection pads of the first interconnect (Fig. 1-3F; first chip 111 connected with first copper column 180 by flip-chip bonding and a second chip 112 connected with second copper column 190 through flip-chip bonding technique).
Claim 3 are rejected under 35 U.S.C. 103 as being unpatentable over Li, CN-107195613, in view of Love, US 5334804 as applied to claim 1-2,4-6 and 8-10 above and further in view of Pokhrel, US 2019/0136369.
Regarding claim 3, Li substantially discloses the invention including PCB package substrate has first set of copper columns on top surface but is specifically silent about the solder bumps have a first coefficient of thermal expansion and the copper has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. However, Pokhrel teaches that a copper pillar bump with the structure of a non-reflowable copper pillar and a reflowable solder cap has the following advantages: (1) copper has low electrical resistance and high current density capability; (2) thermal conductivity of copper provides more than three times the thermal conductivity of solder bump [0003]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Li by providing the solder bumps have a first coefficient of thermal expansion and the copper has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion, so that copper pillars do not collapse during reflow allowing for very fine pitch without compromising stand-off height [0003].
Claim 7 are rejected under 35 U.S.C. 103 as being unpatentable over Li, CN-107195613, in view of Love, US 5334804 as applied to claim 1-2,4-6 and 8-10 above and further in view of Arshad, US 2024/0404973.
Regarding claim 7, Li substantially discloses the invention including PCB package substrate has first set of copper columns on top surface and chips connected with copper column by flip-chip bonding but is specifically silent about an isolation layer made of ABF (Ajinomoto build-up film) disposed on the first interconnect to provide electrical isolation for the die. However, Arshad teaches that at step 407, a first dielectric deposition is performed. The first trace level conductor layer 451 and the first connection level conductor layer 452 are covered in a dielectric material 461. In an example a thermoplastic material is used. In a particular example Ajinomoto build-up film (ABF) is used [0044]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Li by providing an isolation layer made of ABF (Ajinomoto build-up film) disposed on the first interconnect to provide electrical isolation for the die, so that the ABF softens under heat and conforms to the semiconductor wafer and covers the conductors without voids. The ABF can then be cured to harden to form the dielectric material [0044].
Conclusion
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/AZM PARVEZ/
Examiner
Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Prosecution Insights