DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are: the inhibitor i that is adhered to the inner surface of the opening OP1 and the surface of the FP electrode 10 is removed (Fig. 7D and 11D) during the repeated atomic layer deposition process. Removing of inhibitor and/or dangling bonds is an essential method step to forming the gap, as it is not clear in the claim language, how the gap is formed without removing the inhibitor and/or dangling bonds. The repeated adsorption steps of claim 1 would fail to form the gap as claimed without an intervening removal step. Thus the claim is incomplete for failing to include the removal step essential to allowing the repeated atomic layer deposition steps to form the gap at the lower portion of the opening.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec, US 2024/0105784, in view of TABATA, US 2020/0035501.
Regarding claim 1, Siemieniec discloses; a method for manufacturing a semiconductor device, the method comprising: forming an opening in an upper surface of a first semiconductor region of a first conductivity type (Fig. 2A and [0111-0112]; a trench 13 is formed in the upper surface 12 of the semiconductor substrate 11with implantation of dopants into the semiconductor substrate 11) and forming a gap (Fig. 1A, 2J and [0110]; the vacuum-filled or gas-filled cavity) at a lower portion of the opening (Fig. 1A, 2J and [0096]; cavity 20 in the lower part of the trench 13) by performing atomic layer deposition (Fig. 1A, 2A-2J and [0058]; second insulating layer which is used to cap the recess and form the cavity deposited by atomic layer deposition) to form a first insulating layer at an upper portion of the opening so as to plug the opening (Fig. 1A, 2I-2J and [0121]; second insulating layer 55 is deposited onto the first major surface which extends into the upper portion of the trench 13 and which forms the cap 22), the atomic layer deposition including repeatedly performing adsorption of a precursor to an inner surface of the upper portion of the opening (Fig. 2H and [0120, 0123]; dielectric liner layer 54 used to assist in improving the adhesion and for atomic layer deposition (ALD) deposition and in order to prevent material deposition in higher depth x the sticking coefficient of the precursor is elected). Siemieniec substantially discloses the invention of method steps for field plate transistor MOSFET device with sealed cavity in the lower part of the trench but is silent about the method step of adsorption of an inhibitor to an inner surface of the lower portion of the opening, or termination of dangling bonds of a semiconductor material present at the inner surface of the lower portion of the opening. However, TABATA teaches that polymer film P functions as an inhibitor of the atomic layer deposition (ALD) cycle (Fig. 3A-3C, 5 and [0042]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Siemieniec by providing the method step of adsorption of an inhibitor to an inner surface of the lower portion of the opening, or termination of dangling bonds of a semiconductor material present at the inner surface of the lower portion of the opening so that the plasma processing apparatus forms an inhibitor on a bottom surface of the opening through chemical vapor deposition (CVD) to form a first film to which a predetermined gas species is not adsorbed ([0004]).
Regarding claim 2, Siemieniec discloses; forming a gate electrode ([0016]; the trench further includes a gate electrode arranged towards the top of the trench) on the first insulating layer inside the opening after the forming of the gap.
Regarding claim 3, Siemieniec discloses; forming a first layer (Fig. 1A and [0112]; trench 13 is lined with a first insulating sublayer 50a) and a conductive part (Fig. 2D-2H and [0115]; conductive material 51 is then inserted into the trench 13) after the forming of the opening, the first layer (Fig. 1A and [0112]; trench 13 is lined with a first insulating sublayer 50a) being positioned at a bottom portion of the opening, the conductive part (Fig. 2D-2H and [0115]; conductive material 51 is then inserted into the trench 13) being positioned on the first layer, the first insulating layer (Fig. 1A, 2I-2J and [0121]; second insulating layer 55 is deposited onto the first major surface which extends into the upper portion of the trench 13 and which forms the cap 22) being formed along the inner surface of the upper portion of the opening and along an upper surface of the conductive part.
Allowable Subject Matter
Claims 4-5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AZM PARVEZ whose telephone number is (571)272-1447. The examiner can normally be reached M-F 9-6 EST.
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/AZM PARVEZ/
Examiner
Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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