DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1-4, 7, 12-17, is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Kim et al., US 2015/0201495 A1.
Claims 1, 14. Kim et al., discloses a semiconductor package (such as the one in fig. 2, [0025]), comprising:
-a substrate (item 214);
-first and second metal layers (items 220/216), the second metal layer being above the substrate, and the first metal layer being above the second metal layer (as seen in the structure of fig. 2);
-third and fourth metal layers (items 212/208), the third metal layer being below the substrate, and the fourth metal layer being below the third metal layer (as seen in the structure of fig. 2);
-and a plurality of through-substrate vias (TSV) (items 234/236) within the substrate, wherein the semiconductor package includes an input inductor and one or more output inductors (items 224/226/228), wherein the input inductor includes one or more input solenoid loops formed from the first metal layer, an input TSV group, and the fourth metal layer, the input TSV group comprising one or more TSVs of the plurality of TSVs, and wherein each output inductor includes one or more solenoid loops formed from the second metal layer, an output TSV group, and the third metal layer, the output TSV group comprising one or more TSVs of the plurality of TSVs (this limitation would read through [0026] that illustrates a first 3D inductor 224, a second 3D inductor 226 and a third 3D inductor 228 within the device 200. The first 3D inductor 224, the second 3D inductor 226 and/or the third 3D inductor 228 may each be a 3D solenoid inductor).
Claims 2, 15. Kim et al., discloses the semiconductor package of claims 1, 14, wherein the input inductor magnetically couples with at least one output inductor, and wherein the input inductor and the at least one output inductor do not form a circuit (this limitation would read through [0026] wherein is disclosed for example, it will be recognized that other devices may also include the disclosed devices (e.g. 3D solenoid inductors), such as the base stations, switching devices, and network equipment. Further, examiner notes that in many power supply designs, especially in switch‑mode power supplies (SMPS), the input inductor and one output inductor are not connected in a single continuous loop because of the operating principle of the converter topology and the role of each inductor).
Claims 3-4, 7, 16-17. Kim et al., discloses the semiconductor package of claims 1, 14, wherein at least one solenoid loop of at least one output inductor is within the one or more solenoid loops of the input inductor (this limitation would read through [0026] wherein is disclosed for example, upside-down "U" loop for current flow in the third 3D inductor 228 is formed from the LGA 204 coupled to the right package via 206b, through the first conductive layer 208 of the bottom right third inductor region 228a, through the second conductive pillar 213 of the bottom right third inductor region 228a, through the second conductive layer 212 of the bottom right third inductor region 228a, and through the right second substrate package via 236).
Claim 12. Kim et al., discloses the semiconductor package of claim 1, wherein the substrate is any one or more of a laminate substrate, an embedded trace substrate (ETS), or a glass substrate (this limitation would read through [0036] wherein is disclosed for example, the first substrate 202, the second substrate 214 and/or the third substrate 222 may be glass or other materials such as Silicon (Si), Gallium Arsenide (GaAs), Indium Phosphide (InP) Silicon Carbide (SiC), Sapphire (Al.sub.2O.sub.3), Quartz, Silicon on Insulator (SOI), Silicon on Sapphire (SOS), High Resistivity Silicon (HRS), Aluminum Nitride (AlN), a plastic substrate, a laminate, or a combination thereof.
Claim 13. Kim et al., discloses the semiconductor package of claim 1, wherein the semiconductor package is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle (this limitation would read through [0055] wherein is disclosed for example, the remote units may be mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, GPS enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, or other devices that store or retrieve data or computer instructions, or combinations thereof).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
6. Claim(s) 8 and 19, is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US 2015/0201495 A1.
Claims 8 and 19. Kim et al., discloses the semiconductor package of claims 1, 14, but does not specify wherein an inductance of the first output inductor is different from an inductance of the second output inductor, and wherein the one or output inductors includes at least a first output inductor and a second output inductor, and wherein an inductance of the first output inductor is different from an inductance of the second output inductor.
However, [0018] of Kim indicates for example, the substrate thickness is fixed, leading to many design constraints when fabricating the inductor. In addition, 3D solenoid inductors may be magnetically coupled together in one 3D structure, and there may be multiple inductors on the same substrate. Examiner notes that by definition Inductance is a fundamental electrical property of a conductor or circuit that describes its ability to generate an electromotive force (voltage) in response to a change in current flowing through it. According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have an inductance of the first output inductor different from an inductance of the second output inductor its recognized suitability by using inductors with different inductance values which is a deliberate design choice to achieve specific circuit behaviors, performance goals, and functional requirements.
Allowable Subject Matter
7. Claims 5-6, 9-11, 18, 20, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(A) Claim 5, contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the input inductor has no TSV in common with any of the one or more output inductors.
(B) Claim 6, is/are also allowable subject matter, as depend on claim 5.
(C) Claim 9, contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein an input RC in series connection with the input inductor, the input RC comprising an input capacitor in parallel connection with an input resistor; a first output RC in series connection with the first output inductor, the first output RC comprising a first output capacitor in parallel connection with a first output resistor; and a second output RC in series connection with the second output inductor, the second output RC comprising a second output capacitor in parallel connection with a second output resistor.
(D) Claims 10-11, are also allowable subject matter, as depend on claim 9.
(E) Claim 20, contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of patterning the conductive material deposited on the upper and lower surfaces of the substrate to form the second and third metal layers; forming upper and lower passivation layers on upper and lower surfaces of the substrate, respectively; forming holes in the upper and lower passivation layers expose one or more portions of the second and third metal layers; depositing another conductive material to fill the holes of the upper and lower passivation layers, on an upper surface of the upper passivation layer and on a lower surface of the lower passivation layer, wherein the another conductive material filling the holes of the upper passivation layer form one or more upper passivation vias (TPV), and wherein the another conductive material filling the holes of the lower passivation layer form one or more lower TPVs; and patterning the another conductive material deposited on the upper surface of the upper passivation layer and on the lower surface of the lower passivation layer respectively to form the first and fourth metal layers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights