Prosecution Insights
Last updated: July 17, 2026
Application No. 18/649,789

EMBEDDED WAFER LEVEL OPTICAL SENSOR PACKAGING

Non-Final OA §102§Other
Filed
Apr 29, 2024
Priority
Jun 22, 2020 — provisional 63/042,216 +1 more
Examiner
REAMES, MATTHEW L
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
STMicroelectronics N.V.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
844 granted / 1097 resolved
+8.9% vs TC avg
Strong +18% interview lift
Without
With
+18.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
45 currently pending
Career history
1123
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
75.2%
+35.2% vs TC avg
§102
5.2%
-34.8% vs TC avg
§112
11.5%
-28.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1097 resolved cases

Office Action

§102 §Other
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) s 1-2 are is/are rejected under 35 U.S.C. 102a1 as being anticipated by Hillman 20110089531. a. As to claim 1, Hillman teaches A method, comprising: forming an opening extending into a passive portion of a first surface of a wafer (figures 4 and 5 items 102/402 in top of item 500/154); placing an electrical component in the opening such that a surface of the electrical component is substantially co-planar with the first surface of the wafer (figure 7 and 19 item 702 and 120 paragraph 33 the contacts being coplanar would make 120 coplanar so at least that portion of the die is coplanar); and forming a resin between sidewalls of the electrical component and sidewalls of the opening surrounding the electrical component with the resin (item 118 paragraph 25 BCB is a resin). b. As to claim 2, Hillman teaches wherein forming the opening extending into the passive portion of the first surface of the wafer includes forming the opening extending from the first surface of the wafer to a second surface (figure 5 top part of item 500 until it reaches 502_ is the wafer of the wafer opposite to the first surface of the wafer (figure 5 and 19). Allowable Subject Matter Claim 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art fails to teach and or suggest: For claim 3: further comprising: forming a conductive contact on a second surface of the wafer opposite to the first surface of the wafer; forming a bonding wire on the first surface of the wafer coupling the electrical component to an electrical connection on the wafer; forming an optically transmissive material on the electrical component and on the bonding wire; forming a molding compound on the first surface of the wafer covering the optically transmissive material; and forming an opening in the molding compound exposing a surface of the optically transmissive material. For claim 4: further comprising: forming a contact on a second surface of the wafer opposite to the first surface of the wafer; forming a molding compound on the first surface of the wafer; forming a bonding wire in an opening of the molding compound coupling the electrical component to an electrical connection in the wafer; and forming an optically transmissive material on the electrical component, on the bonding wire, and in the opening of the molding compound. Claim 6-20 are allowed. AS to claim 6, prior art fails to teach and or suggest A method, comprising: positioning a light sensor at a first surface of a substrate; forming an opening in the substrate, the opening extending through the first surface of the substrate and a second surface of the substrate; positioning a light emitter in the opening in the substrate; and forming a resin in the opening and on opposite sides of the light emitter. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F. Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW L. REAMES/ Primary Examiner Art Unit 2896 /MATTHEW L REAMES/Primary Examiner, Art Unit 2896
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Prosecution Timeline

Apr 29, 2024
Application Filed
Jun 12, 2026
Non-Final Rejection mailed — §102, §Other (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12684892
COMPOUND SEMICONDUCTOR DEVICE
3y 1m to grant Granted Jul 14, 2026
Patent 12684276
ELECTRONIC DEVICE
2y 5m to grant Granted Jul 14, 2026
Patent 12684972
DISPLAY APPARATUS
2y 9m to grant Granted Jul 14, 2026
Patent 12684776
MEMORY DEVICE
2y 9m to grant Granted Jul 14, 2026
Patent 12684962
DISPLAY PANEL, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING DISPLAY DEVICE
2y 9m to grant Granted Jul 14, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
95%
With Interview (+18.0%)
2y 8m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1097 resolved cases by this examiner. Grant probability derived from career allowance rate.

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