DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claim(s) 1, 2, 5 and 7-9 is/are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by AKIYAMA (2009/0152602), (hereinafter, AKIYAMA).
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RE Claims 1 and 7, AKIYAMA discloses in FIGS. 1-4 a semiconductor device, comprising:
a semiconductor substrate 1 “silicon” having a first surface and a second surface opposite the first surface, referring to FIG. 1A;
an electronic component 8 “transistor”, hence meeting the limitation of Claim 7, at the first surface of the semiconductor substrate 1;
a dielectric structure 6 carried by the first surface of the semiconductor substrate 1 and surrounding the electronic component 8 “transistor”, referring to FIG. 1E;
a conductive interconnect 17 extending through the semiconductor substrate 1 and the dielectric structure 6/11/20, the conductive interconnect 17 having a first end protruding from the first surface of the semiconductor substrate through the dielectric structure 6 and a second end opposite the first end, referring to FIG. 1H; and
a conductive layer 16 carried by the dielectric structure 6/11/20,
wherein the conductive layer 16 is electrically coupled between the first end of the conductive interconnect and the electronic component 8m referring to FIG. 1H, and
wherein a first horizontal plane contains, referring to the annotated FIG. 1I above, at least a portion of a lower surface of the conductive layer 16 and intersects a sidewall of the first end of the conductive interconnect 17, referring to FIG. 1I, as annotated above.
RE Claim 2, AKIYAMA discloses semiconductor device, further comprising a vertical contact 26 positioned in the dielectric structure 6/11/20, wherein the vertical contact 26 is electrically coupled between the conductive layer 16 and the electronic component 8, referring to FIG. 1H.
RE Claim 5, AKIYAMA discloses semiconductor device, wherein the dielectric structure 6/11/20 is a first dielectric structure 6/11/20, wherein the conductive layer 16 is a first conductive layer, and wherein the semiconductor device further comprises:
a second dielectric structure 21/30/31 carried by the first dielectric structure 6/11/20, the first conductive layer 16, and the first end of the conductive interconnect 17; and
a second conductive layer 33 formed in the second dielectric structure 21/30/31,
wherein the second conductive layer 33 is coupled to the first end of the conductive interconnect 17 through a first set of one or more openings in the second dielectric structure 21/30/31, and
wherein the second conductive layer 33 is coupled to the first conductive layer 16 through a second set of one or more openings in the second dielectric structure 21/30/31, referring to FIG. 1I.
RE Claim 8, AKIYAMA discloses semiconductor device, wherein the conductive layer 16 is a first conductive layer, wherein the semiconductor device further comprises
a second conductive layer 43 formed on the second surface of the semiconductor substrate 1, referring to FIG. 1I, and wherein the second conductive layer 43 is in contact with the second end of the conductive interconnect 17.
RE Claim 9, AKIYAMA discloses semiconductor device, wherein the conductive layer 16 is in direct contact with the conductive interconnect 17. Examiner notes the conductive barrier layers 15 and 13 are considered part of the conductor interconnect 17 and conductive interconnect 16 respectively, hence the claimed limitation is met.
Claim(s) 1 and 6 is/are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Chung et al. (US 2007/0152349), (hereinafter, Chung).
RE Claims 1, Chung discloses in FIGS. 1-22 a semiconductor device with wafer-level packaging and a method of making the same. Chung discloses a semiconductor device, comprising:
a semiconductor substrate 30 having a first surface and a second surface opposite the first surface, referring to FIG. 12;
an electronic component in a “device region”, at the first surface of the semiconductor substrate 30. Examiner notes since the entire disclosure of Chung’s disclosure is directed to a wafer-level packing with interconnect structure to device regions [0049 and 0051], which implies and electronic component, hence meeting the claimed limitation;
a dielectric structure 36/38a carried by the first surface of the semiconductor substrate 30 and surrounding the electronic component a “device region”, referring to FIG. 12;
a conductive interconnect 40b extending through the semiconductor substrate 30 and the dielectric structure 36/38a, the conductive interconnect 40b having a first end protruding from the first surface of the semiconductor substrate 30 through the dielectric structure 36/38a and a second end opposite the first end, referring to FIG. 12; and
a conductive layer 40a carried by the dielectric structure 36/38a,
wherein the conductive layer 40a is electrically coupled between the first end of the conductive interconnect 40b and the electronic component “a device region” referring to FIG. 12, and
wherein a first horizontal plane contains, referring to FIG. 12 above, at least a portion of a lower surface of the conductive layer 40a and intersects a sidewall of the first end of the conductive interconnect 40, referring to FIG. 12. It is the examiner position that the two portions 40a and 40b forming the conductive layer and conductive interconnect are joined together, hence meeting the claimed limitation.
RE Claim 6, AKIYAMA discloses semiconductor device, wherein:
the dielectric structure 36/38a is a first dielectric structure; and
the semiconductor device further comprises a second dielectric structure 72, referring to FIGS. 10 and 12 carried by the first dielectric structure 36/38a, wherein the conductive interconnect 40b extends at least partially through the second dielectric structure 72, referring to FIG. 12, and
wherein the conductive layer 40a is formed at least partially in the second dielectric structure 72, referring to FIG. 12.
Allowable Subject Matter
Claims 10-15 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including etching of the coating prior to applying the loosening agent as disclosed in Claim 10.
Claims 3 and 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) Claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
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