Prosecution Insights
Last updated: April 19, 2026
Application No. 18/649,986

SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT

Non-Final OA §112
Filed
Apr 29, 2024
Examiner
ABDELAZIEZ, YASSER A
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology, Inc.
OA Round
3 (Non-Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
2y 3m
To Grant
89%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
687 granted / 798 resolved
+18.1% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
34 currently pending
Career history
832
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
46.5%
+6.5% vs TC avg
§102
30.4%
-9.6% vs TC avg
§112
18.5%
-21.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 798 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application is being examined under the pre-AIA first to invent provisions. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the portion of a lower surface of the conductive layer that is coplanar with a sidewall of the first end of the conductive interconnect.” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-9 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. In the instant case, nowhere in the disclosure a portion of a lower surface of the conductive layer that is shown to be coplanar with a sidewall of the first end of the conductive interconnect, as to enable one of ordinary skill in the art, at the effective filing date, to make and use the claimed invention or to determine the mete and bound of the claimed invention. Furthermore, applicant argument did not point, in the remarks, as to which portion of the disclosure/drawings cover the newly added limitations. Applicant clarification is required. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. PNG media_image1.png 450 403 media_image1.png Greyscale In the instant case, Claim 1 disclose “a portion of a lower surface of the conductive layer is coplanar with a sidewall of the first end of the conductive interconnect.” First, examiner has a representation of what the “claimed limitations” may be represented. The plain “abcd” represents a vertical cross-section in the conductive layer carried by the dielectric structure, while the plain “efgh” is a vertical cross-section in the conductive interconnect, wherein the vertical line “dc” represents a line in a plain that is perpendicular to the plain, where the sidewall “eh” of a different plain. Therefore, according the drawings above, the portion of a lower surface of the conductive layer cannot be coplanar with a sidewall of the first end of the conductive interconnect, since the lower surface of the conductive layer carried by the dielectric structure is perpendicular to the sidewall of the sidewall of the first end of the conductive interconnect. Furthermore, the intersection of lower surface “cd” and the sidewall “eh”, i.e. point e/d, is co-linear, NOT co-planar with the points “ad/eh”. Therefore, applicant claimed limitation portion of a lower surface of the conductive layer is coplanar with a sidewall of the first end of the conductive interconnect is confusing and does not conform with the disclosed invention. Applicant clarification is required. Allowable Subject Matter Claims 10-15 are allowed. The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including etching of the coating prior to applying the loosening agent as disclosed in Claim 10. In the instant case, Cobbley et al. (US 2009/0294983) disclose a conductive via of a semiconductor device includes a relatively small diameter portion extending into an active surface of a fabrication substrate and a corresponding, relatively large diameter portion that extends into a back side of the fabrication substrate. The conductive via may be fabricated by forming the relatively small diameter portion before or during BEOL processing, while the large diameter portion of each conductive via may be fabricated after BEOL processing is complete. CHUNG et al. (US 2012/0104608) discloses a package has two semiconductor devices having a semiconductor substrate (30). A conductive interconnect (40) corresponding to the semiconductor substrate is provided with horizontal portion (40a) and vertical portion (40b) that are arranged on surfaces of the semiconductor substrate. An air gap (70) is provided between a sidewall of the vertical portion of the conductive interconnect and semiconductor substrate. The semiconductor devices are coupled with each other through the conductive interconnect. Examiner notes that the metal routing layer 40a includes a first surface in contact with the dielectric structure 38a and a second surface opposite the first surface, referring to FIG. 12, and wherein the first surface is NOT beneath an upper surface of the conductive interconnect 40b such that at least a portion of the metal routing layer is coplanar with the first end region of the conductive interconnect 40b. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Manno Jessica can be reached at (571)272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Apr 29, 2024
Application Filed
Jul 07, 2025
Non-Final Rejection — §112
Jul 07, 2025
Examiner Interview (Telephonic)
Sep 18, 2025
Response Filed
Sep 23, 2025
Final Rejection — §112
Nov 25, 2025
Response after Non-Final Action
Dec 17, 2025
Request for Continued Examination
Jan 07, 2026
Response after Non-Final Action
Jan 10, 2026
Non-Final Rejection — §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
89%
With Interview (+3.3%)
2y 3m
Median Time to Grant
High
PTA Risk
Based on 798 resolved cases by this examiner. Grant probability derived from career allow rate.

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